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«
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[PULL,v3,19/35] bsd-user: Implement RISC-V CPU initialization and main loop
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,18/35] hw/intc: riscv-imsic: Fix interrupt state updates.
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,16/35] target/riscv32: Fix masking of physical address
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 2 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,15/35] target: riscv: Add Svvptc extension support
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,14/35] hw/riscv: Respect firmware ELF entry point
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,13/35] target/riscv: Add textra matching condition for the triggers
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,12/35] target/riscv: Preliminary textra trigger CSR writting support
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 2 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,09/35] target/riscv: Stop timer with infinite timecmp
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,08/35] target/riscv/kvm: Fix the group bit setting of AIA
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,06/35] target/riscv: fix za64rs enabling
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 2 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,04/35] tests/acpi: Add expected ACPI SRAT AML file for RISC-V
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
1 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,03/35] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
1 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
1 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
[PULL,v3,01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
- 1 -
-
-
-
2024-10-02
Alistair Francis
New
[PULL,v3,00/35] riscv-to-apply queue
- - -
-
-
-
2024-10-02
Alistair Francis
New
{PATCH] accel/tcg: Fix CPU specific unaligned behaviour
{PATCH] accel/tcg: Fix CPU specific unaligned behaviour
- - -
-
-
-
2024-10-02
Helge Deller
New
[v8,12/12] docs/specs: add riscv-iommu
riscv: QEMU RISC-V IOMMU Support
- 1 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,11/12] qtest/riscv-iommu-test: add init queues test
riscv: QEMU RISC-V IOMMU Support
1 1 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,10/12] hw/riscv/riscv-iommu: add DBG support
riscv: QEMU RISC-V IOMMU Support
- 2 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,09/12] hw/riscv/riscv-iommu: add ATS support
riscv: QEMU RISC-V IOMMU Support
1 1 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
riscv: QEMU RISC-V IOMMU Support
1 1 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,07/12] test/qtest: add riscv-iommu-pci tests
riscv: QEMU RISC-V IOMMU Support
1 1 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,06/12] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
riscv: QEMU RISC-V IOMMU Support
- 2 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,05/12] hw/riscv: add riscv-iommu-pci reference device
riscv: QEMU RISC-V IOMMU Support
- 2 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,04/12] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
riscv: QEMU RISC-V IOMMU Support
- 2 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,03/12] hw/riscv: add RISC-V IOMMU base emulation
riscv: QEMU RISC-V IOMMU Support
1 - -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,02/12] hw/riscv: add riscv-iommu-bits.h
riscv: QEMU RISC-V IOMMU Support
- 3 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v8,01/12] exec/memtxattr: add process identifier to the transaction attributes
riscv: QEMU RISC-V IOMMU Support
- 3 -
-
-
-
2024-10-02
Daniel Henrique Barboza
New
[v2,2/2] {hw/arm,docs/system/arm}: Add SPI to Allwinner A10
Allwinner A10 SPI controller emulation
- - -
-
-
-
2024-10-01
Strahinja Jankovic
New
[v2,1/2] hw/ssi: Allwinner A10 SPI emulation
Allwinner A10 SPI controller emulation
- - -
-
-
-
2024-10-01
Strahinja Jankovic
New
linux-user: Trace wait4()'s and waitpid()'s wstatus
linux-user: Trace wait4()'s and waitpid()'s wstatus
- 1 -
-
-
-
2024-10-01
Ilya Leoshkevich
New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier
[v3] virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-23
Srujana Challa
Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier
[v2] virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-20
Srujana Challa
Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier
virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-12
Srujana Challa
Changes Requested
cryptodev-vhost-user: add asymmetric crypto support
cryptodev-vhost-user: add asymmetric crypto support
- - -
-
-
-
2023-05-14
Gowrishankar Muthukrishnan
Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions
[v1,1/2] target/riscv: add Zicond as an experimental extension
- - -
-
-
-
2023-01-20
Philipp Tomsich
Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension
[v1,1/2] target/riscv: add Zicond as an experimental extension
- - -
-
-
-
2023-01-20
Philipp Tomsich
Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-24
Lev Kujawski
Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-24
Lev Kujawski
Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
1 - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[v1] error-report: fix g_date_time_format assertion
[v1] error-report: fix g_date_time_format assertion
- - -
-
-
-
2022-04-24
Wang, Haiyue
Superseded
[v1] aio-posix: fix build failure io_uring 2.2
[v1] aio-posix: fix build failure io_uring 2.2
- - -
-
-
-
2022-02-17
Wang, Haiyue
Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension
[v2,1/2] target/riscv: iterate over a table of decoders
- - -
-
-
-
2022-01-13
Philipp Tomsich
Superseded
[v2,1/2] target/riscv: iterate over a table of decoders
[v2,1/2] target/riscv: iterate over a table of decoders
- - -
-
-
-
2022-01-13
Philipp Tomsich
Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension
[v1,1/2] decodetree: Add an optional predicate-function for decoding
- - -
-
-
-
2022-01-09
Philipp Tomsich
Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding
[v1,1/2] decodetree: Add an optional predicate-function for decoding
- - -
-
-
-
2022-01-09
Philipp Tomsich
Superseded
target/riscv: Fix position of 'experimental' comment
target/riscv: Fix position of 'experimental' comment
- 3 -
-
-
-
2022-01-06
Philipp Tomsich
Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 - -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs])
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- - -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw()
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 - -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs]
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,07/14] target/riscv: Add instructions of the Zbc-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
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