Show patches with: Archived = No       |   2808 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,02/49] tests: add 'rust' and 'bindgen' to CI package list [PULL,01/49] stubs: avoid duplicate symbols in libqemuutil.a - - - --- 2024-10-31 Paolo Bonzini New
[PULL,01/49] stubs: avoid duplicate symbols in libqemuutil.a [PULL,01/49] stubs: avoid duplicate symbols in libqemuutil.a - 1 1 --- 2024-10-31 Paolo Bonzini New
[PULL,00/49] i386, qom, build changes for 2024-10-31 - - - --- 2024-10-31 Paolo Bonzini New
[PULL,14/14] tests/functional: Convert the riscv_opensbi avocado test into a standalone test [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 2 1 --- 2024-10-31 Thomas Huth New
[PULL,13/14] tests/functional: Convert the OrangePi tests to the functional framework [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - - - --- 2024-10-31 Thomas Huth New
[PULL,12/14] tests/functional: Convert BananaPi tests to the functional framework [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - - - --- 2024-10-31 Thomas Huth New
[PULL,11/14] tests/functional: Convert the tcg_plugins test [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - - - --- 2024-10-31 Thomas Huth New
[PULL,10/14] next-cube: remove cpu parameter from next_scsi_init() [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 1 - --- 2024-10-31 Thomas Huth New
[PULL,09/14] next-cube: fix up compilation when DEBUG_NEXT is enabled [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 1 - --- 2024-10-31 Thomas Huth New
[PULL,08/14] hw/s390x: Re-enable the pci-bridge device on s390x [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 3 - --- 2024-10-31 Thomas Huth New
[PULL,07/14] tests/functional: Fix the s390x and ppc64 tuxrun tests [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - - - --- 2024-10-31 Thomas Huth New
[PULL,06/14] tests/vm/openbsd: Remove the "Time appears wrong" workaround [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - - - --- 2024-10-31 Thomas Huth New
[PULL,05/14] tests/functional: Add a test for sh4eb [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 1 - --- 2024-10-31 Thomas Huth New
[PULL,04/14] Revert "Remove the unused sh4eb target" [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 2 - --- 2024-10-31 Thomas Huth New
[PULL,03/14] tests/functional: make cached asset files read-only [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 2 1 --- 2024-10-31 Thomas Huth New
[PULL,02/14] tests/functional: make tuxrun disk images writable [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job - 1 - --- 2024-10-31 Thomas Huth New
[PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job [PULL,01/14] .gitlab-ci.d/cirrus: Remove the macos-15 job 1 1 - --- 2024-10-31 Thomas Huth New
[PULL,00/14] Misc patches (functional tests, next-cube machine, ...) - - - --- 2024-10-31 Thomas Huth New
[RFC,5/5] qom: enforce use of static, const string with object_new() RFC: require error handling for dynamically created objects - - - --- 2024-10-31 Daniel P. Berrangé New
[RFC,4/5] qom: introduce object_new_dynamic() RFC: require error handling for dynamically created objects - - - --- 2024-10-31 Daniel P. Berrangé New
[RFC,3/5] convert code to object_new_dynamic() where appropriate RFC: require error handling for dynamically created objects - - - --- 2024-10-31 Daniel P. Berrangé New
[RFC,2/5] qom: allow failure of object_new_with_class RFC: require error handling for dynamically created objects - - - --- 2024-10-31 Daniel P. Berrangé New
[RFC,1/5] qom: refactor checking abstract property when creating instances RFC: require error handling for dynamically created objects - - - --- 2024-10-31 Daniel P. Berrangé New
target/i386/hvf: fix handling of XSAVE-related CPUID bits target/i386/hvf: fix handling of XSAVE-related CPUID bits - - - --- 2024-10-31 Paolo Bonzini New
[v3,8/8] target/i386: Introduce GraniteRapids-v2 model Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-31 Tao Su New
[v3,7/8] target/i386: Add AVX512 state when AVX10 is supported Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-31 Tao Su New
[v3,6/8] target/i386: Add feature dependencies for AVX10 Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-31 Tao Su New
[v3,5/8] target/i386: add CPUID.24 features for AVX10 Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-31 Tao Su New
[v3,4/8] target/i386: add AVX10 feature and AVX10 version property Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 1 --- 2024-10-31 Tao Su New
[v3,3/8] target/i386: return bool from x86_cpu_filter_features Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 - --- 2024-10-31 Tao Su New
[v3,2/8] target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 - --- 2024-10-31 Tao Su New
[v3,1/8] target/i386: cpu: set correct supported XCR0 features for TCG Add AVX10.1 CPUID support and GraniteRapids-v2 model - 1 - --- 2024-10-31 Tao Su New
hw/loongarch/virt: Add reset interface for virt-machine hw/loongarch/virt: Add reset interface for virt-machine 1 - - --- 2024-10-31 bibo mao New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier [v3] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-23 Srujana Challa Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier [v2] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-20 Srujana Challa Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-12 Srujana Challa Changes Requested
cryptodev-vhost-user: add asymmetric crypto support cryptodev-vhost-user: add asymmetric crypto support - - - --- 2023-05-14 Gowrishankar Muthukrishnan Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM 1 - - --- 2022-06-16 Lev Kujawski Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[v1] error-report: fix g_date_time_format assertion [v1] error-report: fix g_date_time_format assertion - - - --- 2022-04-24 Wang, Haiyue Superseded
[v1] aio-posix: fix build failure io_uring 2.2 [v1] aio-posix: fix build failure io_uring 2.2 - - - --- 2022-02-17 Wang, Haiyue Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - 3 - --- 2022-01-06 Philipp Tomsich Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw() target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-03 Philipp Tomsich Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,04/14] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
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