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Apply
«
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[1/3] hw/nvram: Add BCM2835 OTP device
Initial support for One-Time Programmable Memory (OTP) in BCM2835
- - -
-
-
-
2024-05-10
Rayhan Faizel
New
[v3,5/5] blockdev: mirror: check for target's cluster size when using bitmap
mirror: allow specifying working bitmap
- - -
-
-
-
2024-05-10
Fiona Ebner
New
[v3,4/5] iotests: add test for bitmap mirror
mirror: allow specifying working bitmap
- - -
-
-
-
2024-05-10
Fiona Ebner
New
[v3,3/5] mirror: allow specifying working bitmap
mirror: allow specifying working bitmap
1 - -
-
-
-
2024-05-10
Fiona Ebner
New
[v3,2/5] block/mirror: replace is_none_mode with sync_mode in MirrorBlockJob struct
mirror: allow specifying working bitmap
- - -
-
-
-
2024-05-10
Fiona Ebner
New
[v3,1/5] qapi/block-core: avoid the re-use of MirrorSyncMode for backup
mirror: allow specifying working bitmap
1 1 -
-
-
-
2024-05-10
Fiona Ebner
New
[RFC] scripts/update-linux-header.sh: be more src tree friendly
[RFC] scripts/update-linux-header.sh: be more src tree friendly
- - -
-
-
-
2024-05-10
Alex Bennée
New
[v2,7/7] hw/xen: Register framebuffer backend via xen_backend_init()
hw/xen: Simplify legacy backends handling
- 1 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,6/7] hw/xen: register legacy backends via xen_backend_init
hw/xen: Simplify legacy backends handling
- 2 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,5/7] hw/xen: initialize legacy backends from xen_bus_init()
hw/xen: Simplify legacy backends handling
- 2 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,4/7] hw/xen: Make XenDevOps structures const
hw/xen: Simplify legacy backends handling
- 1 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,3/7] hw/xen: Constify xenstore_be::XenDevOps
hw/xen: Simplify legacy backends handling
- 1 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,2/7] hw/xen: Constify XenLegacyDevice::XenDevOps
hw/xen: Simplify legacy backends handling
- 1 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
[v2,1/7] hw/xen: Remove declarations left over in 'xen-legacy-backend.h'
hw/xen: Simplify legacy backends handling
- 1 -
-
-
-
2024-05-10
Philippe Mathieu-Daudé
New
tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs
tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regs
- 1 1
-
-
-
2024-05-10
Richard Henderson
New
[v3] hw/virtio: Fix obtain the buffer id from the last descriptor
[v3] hw/virtio: Fix obtain the buffer id from the last descriptor
1 2 -
-
-
-
2024-05-10
Wafer
New
[5/5] target/riscv: Reserve exception codes for sw-check and hw-err
target/riscv: Support RISC-V privilege 1.13 spec
- 2 -
-
-
-
2024-05-10
Fea.Wang
New
[4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
target/riscv: Support RISC-V privilege 1.13 spec
- 2 -
-
-
-
2024-05-10
Fea.Wang
New
[3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
target/riscv: Support RISC-V privilege 1.13 spec
- 2 -
-
-
-
2024-05-10
Fea.Wang
New
[2/5] target/riscv: Support the version for ss1p13
target/riscv: Support RISC-V privilege 1.13 spec
- 3 -
-
-
-
2024-05-10
Fea.Wang
New
[1/5] target/riscv: Reuse the conversion function of priv_spec and string
target/riscv: Support RISC-V privilege 1.13 spec
- 2 -
-
-
-
2024-05-10
Fea.Wang
New
[PULL,8/8] tests/qtest: Add some test cases support on LoongArch
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- - -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,7/8] qemu-options: Deprecate "-runas" and introduce "-run-with user=..." instead
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,6/8] target/s390x: flag te and cte as deprecated
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,5/8] target/s390x: report deprecated-props in cpu-model-expansion reply
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
1 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,4/8] s390x/sclp: Simplify get_sclp_device()
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,3/8] s390x/event-facility: Simplify sclp_get_event_facility_bus()
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,2/8] s390x: Introduce a SCLPDevice pointer under the machine
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 1 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
[PULL,1/8] hw/s390x: Attach the sclpconsole to /machine/sclp/s390-sclp-event-facility
- 4 -
-
-
-
2024-05-10
Thomas Huth
New
[PULL,0/8] s390x and misc patches
- - -
-
-
-
2024-05-10
Thomas Huth
New
fix: correct typo in ext_zvkb configuration variable Signed-off-by: Kaiyao Duan <inspiremenow@muren…
fix: correct typo in ext_zvkb configuration variable Signed-off-by: Kaiyao Duan <inspiremenow@muren…
- - -
-
-
-
2024-05-10
inspireMeNow
New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier
[v3] virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-23
Srujana Challa
Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier
[v2] virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-20
Srujana Challa
Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier
virtio-pci: correctly set virtio pci queue mem multiplier
- - -
-
-
-
2024-02-12
Srujana Challa
Changes Requested
cryptodev-vhost-user: add asymmetric crypto support
cryptodev-vhost-user: add asymmetric crypto support
- - -
-
-
-
2023-05-14
Gowrishankar Muthukrishnan
Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions
[v1,1/2] target/riscv: add Zicond as an experimental extension
- - -
-
-
-
2023-01-20
Philipp Tomsich
Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension
[v1,1/2] target/riscv: add Zicond as an experimental extension
- - -
-
-
-
2023-01-20
Philipp Tomsich
Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-24
Lev Kujawski
Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-24
Lev Kujawski
Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
1 - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM
- - -
-
-
-
2022-06-16
Lev Kujawski
Superseded
[v1] error-report: fix g_date_time_format assertion
[v1] error-report: fix g_date_time_format assertion
- - -
-
-
-
2022-04-24
Wang, Haiyue
Superseded
[v1] aio-posix: fix build failure io_uring 2.2
[v1] aio-posix: fix build failure io_uring 2.2
- - -
-
-
-
2022-02-17
Wang, Haiyue
Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 2 -
-
-
-
2022-01-31
Philipp Tomsich
Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- - -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-30
Philipp Tomsich
Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,5/7] target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
target/riscv: Add XVentanaCondOps and supporting infrastructure changes
- 1 -
-
-
-
2022-01-28
Philipp Tomsich
Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension
[v2,1/2] target/riscv: iterate over a table of decoders
- - -
-
-
-
2022-01-13
Philipp Tomsich
Superseded
[v2,1/2] target/riscv: iterate over a table of decoders
[v2,1/2] target/riscv: iterate over a table of decoders
- - -
-
-
-
2022-01-13
Philipp Tomsich
Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension
[v1,1/2] decodetree: Add an optional predicate-function for decoding
- - -
-
-
-
2022-01-09
Philipp Tomsich
Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding
[v1,1/2] decodetree: Add an optional predicate-function for decoding
- - -
-
-
-
2022-01-09
Philipp Tomsich
Superseded
target/riscv: Fix position of 'experimental' comment
target/riscv: Fix position of 'experimental' comment
- 3 -
-
-
-
2022-01-06
Philipp Tomsich
Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 - -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs])
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 2 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- - -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw()
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 3 -
-
-
-
2021-09-04
Philipp Tomsich
Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions
target/riscv: Update QEmu for Zb[abcs] 1.0.0
1 - -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs]
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,07/14] target/riscv: Add instructions of the Zbc-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,06/14] target/riscv: Reassign instructions to the Zbs-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,04/14] target/riscv: Remove the W-form instructions from Zbs
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
[v9,02/14] target/riscv: Reassign instructions to the Zba-extension
target/riscv: Update QEmu for Zb[abcs] 1.0.0
- 2 -
-
-
-
2021-09-03
Philipp Tomsich
Superseded
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