Show patches with: Archived = No       |   3711 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v8,04/10] virtio-gpu: Support asynchronous fencing Support virtio-gpu DRM native context 1 2 1 --- 2025-02-09 Dmitry Osipenko New
[v8,03/10] virtio-gpu: Handle virgl fence creation errors Support virtio-gpu DRM native context 1 1 1 --- 2025-02-09 Dmitry Osipenko New
[v8,02/10] ui/sdl2: Implement dpy dmabuf functions Support virtio-gpu DRM native context 1 1 1 --- 2025-02-09 Dmitry Osipenko New
[v8,01/10] ui/sdl2: Restore original context after new context creation Support virtio-gpu DRM native context 1 1 1 --- 2025-02-09 Dmitry Osipenko New
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX - 1 - --- 2025-02-09 Bernhard Beschow New
[RFC,4/4] hw/arm/virt: enable VGA hvf: use TCG emulation to handle data aborts - - - --- 2025-02-09 Joelle van Dyne New
[RFC,3/4] hvf: arm: emulate instruction when ISV=0 hvf: use TCG emulation to handle data aborts - - - --- 2025-02-09 Joelle van Dyne New
[RFC,2/4] cpu-target: support emulation from non-TCG accels hvf: use TCG emulation to handle data aborts - - - --- 2025-02-09 Joelle van Dyne New
[RFC,1/4] cpu-exec: support single-step without debug hvf: use TCG emulation to handle data aborts - - - --- 2025-02-09 Joelle van Dyne New
hvf: arm: sign extend when SSE=1 hvf: arm: sign extend when SSE=1 - - - --- 2025-02-09 Joelle van Dyne New
[PULL,9/9] meson: Deprecate 32-bit host support [PULL,1/9] meson: Drop tcg as a module - 3 - --- 2025-02-08 Richard Henderson New
[PULL,8/9] meson: Disallow 64-bit on 32-bit emulation [PULL,1/9] meson: Drop tcg as a module - 2 - --- 2025-02-08 Richard Henderson New
[PULL,7/9] target/*: Remove TARGET_LONG_BITS from cpu-param.h [PULL,1/9] meson: Drop tcg as a module - 3 - --- 2025-02-08 Richard Henderson New
[PULL,6/9] configure: Define TARGET_LONG_BITS in configs/targets/*.mak [PULL,1/9] meson: Drop tcg as a module - 2 - --- 2025-02-08 Richard Henderson New
[PULL,5/9] gitlab-ci: Replace aarch64 with arm in cross-i686-tci build [PULL,1/9] meson: Drop tcg as a module - 2 - --- 2025-02-08 Richard Henderson New
[PULL,4/9] meson: Disallow 64-bit on 32-bit HVF/NVMM/WHPX emulation [PULL,1/9] meson: Drop tcg as a module - 1 - --- 2025-02-08 Richard Henderson New
[PULL,3/9] meson: Disallow 64-bit on 32-bit Xen emulation [PULL,1/9] meson: Drop tcg as a module - 2 - --- 2025-02-08 Richard Henderson New
[PULL,2/9] meson: Disallow 64-bit on 32-bit KVM emulation [PULL,1/9] meson: Drop tcg as a module - 2 - --- 2025-02-08 Richard Henderson New
[PULL,1/9] meson: Drop tcg as a module [PULL,1/9] meson: Drop tcg as a module - 3 - --- 2025-02-08 Richard Henderson New
[PULL,0/9] meson: Disallow 64-bit on 32-bit emulation - - - --- 2025-02-08 Richard Henderson New
[v6,7/7] hw/char/pl011: Implement TX FIFO hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,6/7] hw/char/pl011: Drain TX FIFO when no backend connected hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,5/7] hw/char/pl011: Consider TX FIFO overrun error hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,4/7] hw/char/pl011: Trace FIFO enablement hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,3/7] hw/char/pl011: Introduce pl011_xmit() as GSource hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,2/7] hw/char/pl011: Add transmit FIFO to PL011State hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v6,1/7] hw/char/pl011: Warn when using disabled receiver hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop - 1 - --- 2025-02-08 Philippe Mathieu-Daudé New
[v5,4/4] virtio: Convert feature properties to OnOffAuto virtio: Convert feature properties to OnOffAuto - - - --- 2025-02-08 Akihiko Odaki New
[v5,3/4] qdev-properties: Add DEFINE_PROP_ON_OFF_AUTO_BIT64() virtio: Convert feature properties to OnOffAuto - - - --- 2025-02-08 Akihiko Odaki New
[v5,2/4] qapi: Accept bool for OnOffAuto and OnOffSplit virtio: Convert feature properties to OnOffAuto - - - --- 2025-02-08 Akihiko Odaki New
[v5,1/4] qapi: Do not consume a value if failed virtio: Convert feature properties to OnOffAuto - - - --- 2025-02-08 Akihiko Odaki New
[V2] target/loongarch: fix vcpu reset command word issue [V2] target/loongarch: fix vcpu reset command word issue - - - --- 2025-02-08 Xianglai Li New
[V2] target/loongarch: fix vcpu reset command word issue [V2] target/loongarch: fix vcpu reset command word issue - - - --- 2025-02-08 Xianglai Li New
[3/3] hw/loongarch/virt: Add separate file for fdt building hw/loongarch/virt: Code cleanup - - - --- 2025-02-08 Bibo Mao New
[2/3] hw/loongarch/virt: Rename function prefix name hw/loongarch/virt: Code cleanup - - - --- 2025-02-08 Bibo Mao New
[1/3] hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build hw/loongarch/virt: Code cleanup - - - --- 2025-02-08 Bibo Mao New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier [v3] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-23 Srujana Challa Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier [v2] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-20 Srujana Challa Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-12 Srujana Challa Changes Requested
cryptodev-vhost-user: add asymmetric crypto support cryptodev-vhost-user: add asymmetric crypto support - - - --- 2023-05-14 Gowrishankar Muthukrishnan Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM 1 - - --- 2022-06-16 Lev Kujawski Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[v1] error-report: fix g_date_time_format assertion [v1] error-report: fix g_date_time_format assertion - - - --- 2022-04-24 Wang, Haiyue Superseded
[v1] aio-posix: fix build failure io_uring 2.2 [v1] aio-posix: fix build failure io_uring 2.2 - - - --- 2022-02-17 Wang, Haiyue Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - 3 - --- 2022-01-06 Philipp Tomsich Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw() target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-03 Philipp Tomsich Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
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