Show patches with: Archived = No       |   3689 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[3/3] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[v2,1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[v2,2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[v2,3/3] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-18 Philipp Tomsich Superseded
[v3,01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,02/15] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,04/15] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,06/15] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,07/15] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v3,08/15] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,10/15] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,11/15] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,13/15] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v3,14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v3,15/15] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v4,01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,02/14] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,04/14] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v4,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v4,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v5,01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,02/14] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,04/14] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-23 Philipp Tomsich Superseded
[v5,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-23 Philipp Tomsich Superseded
[v5,01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,02/14] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,04/14] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v5,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-25 Philipp Tomsich Superseded
[v6,01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,02/14] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,04/14] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,06/14] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,07/14] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 1 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-08-25 Philipp Tomsich Superseded
[v6,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-08-25 Philipp Tomsich Superseded
hw/intc/sifive_clint: Fix expiration time logic hw/intc/sifive_clint: Fix expiration time logic - - - --- 2021-08-28 s101062801 New
[v2] hw/intc/sifive_clint: Fix expiration time logic [v2] hw/intc/sifive_clint: Fix expiration time logic - - - --- 2021-08-29 s101062801 New
[v3,1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources QEMU RISC-V ACLINT Support - 2 - --- 2021-08-29 Anup Patel New
[v3,2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT QEMU RISC-V ACLINT Support - 1 - --- 2021-08-29 Anup Patel New
[v3,3/4] hw/riscv: virt: Re-factor FDT generation QEMU RISC-V ACLINT Support - 2 - --- 2021-08-29 Anup Patel New
[v3,4/4] hw/riscv: virt: Add optional ACLINT support to virt machine QEMU RISC-V ACLINT Support - 2 - --- 2021-08-29 Anup Patel New
[1/3] escc: checkpatch fixes escc: fix R_STATUS when SDLC mode is enabled - 1 - --- 2021-08-29 Mark Cave-Ayland New
[2/3] escc: fix R_STATUS channel reset value escc: fix R_STATUS when SDLC mode is enabled - - - --- 2021-08-29 Mark Cave-Ayland New
[3/3] escc: fix STATUS_SYNC bit in R_STATUS register escc: fix R_STATUS when SDLC mode is enabled - 1 - --- 2021-08-29 Mark Cave-Ayland New
[1/3] configure: Add the possibility to read options from meson_options.txt Use meson_options.txt in the configure script - - - --- 2021-08-29 Thomas Huth New
[2/3] configure: Remove options that can be handled via meson_options.txt instead Use meson_options.txt in the configure script - 1 - --- 2021-08-29 Thomas Huth New
[3/3] configure: Get help text from meson_options.txt Use meson_options.txt in the configure script - - - --- 2021-08-29 Thomas Huth New
[v10,1/7,RISCV_PM] Add J-extension into RISC-V RISC-V Pointer Masking implementation - 2 - --- 2021-08-29 Alexey Baturo New
[v10,2/7,RISCV_PM] Add CSR defines for RISC-V PM extension RISC-V Pointer Masking implementation - 1 - --- 2021-08-29 Alexey Baturo New
[v10,3/7,RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode RISC-V Pointer Masking implementation - - - --- 2021-08-29 Alexey Baturo New
[v10,4/7,RISCV_PM] Print new PM CSRs in QEMU logs RISC-V Pointer Masking implementation - 2 - --- 2021-08-29 Alexey Baturo New
[v10,5/7,RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions RISC-V Pointer Masking implementation - 2 - --- 2021-08-29 Alexey Baturo New
[v10,6/7,RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension RISC-V Pointer Masking implementation - 2 - --- 2021-08-29 Alexey Baturo New
[v10,7/7,RISCV_PM] Allow experimental J-ext to be turned on RISC-V Pointer Masking implementation - 1 - --- 2021-08-29 Alexey Baturo New
[v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 1 --- 2021-08-30 Alistair Francis New
[v3,2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 1 --- 2021-08-30 Alistair Francis New
[v3,3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 2 - --- 2021-08-30 Alistair Francis New
[v3,4/5] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines [v3,1/5] target/riscv: Expose interrupt pending bits as GPIO lines - 3 1 --- 2021-08-30 Alistair Francis New
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