Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,00/63] riscv-to-apply queue - - - --- 2020-06-26 Alistair Francis New
[PULL,v2,32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,28/32] target/riscv: Rename IBEX CPU init routine [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,25/32] hw/riscv: sifive_u: Add reset functionality [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,23/32] hw/riscv: sifive_u: Hook a GPIO controller [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,21/32] hw/riscv: sifive_gpio: Clean up the codes [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,20/32] hw/riscv: sifive_u: Generate device tree node for OTP [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,16/32] target/riscv: Use a smaller guess size for no-MMU PMP [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,15/32] riscv/opentitan: Connect the UART device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,v2,14/32] riscv/opentitan: Connect the PLIC device [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,v2,13/32] hw/intc: Initial commit of lowRISC Ibex PLIC [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,12/32] hw/char: Initial commit of Ibex UART [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,11/32] riscv/opentitan: Fix the ROM size [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - - --- 2020-06-19 Alistair Francis New
[PULL,v2,10/32] target/riscv: Implement checks for hfence [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,09/32] target/riscv: Move the hfence instructions to the rvh decode [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,08/32] target/riscv: Report errors validating 2nd-stage PTEs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,06/32] riscv: Keep the CPU init routine names consistent [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,05/32] riscv: Generalize CPU init routine for the imacu CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,04/32] riscv: Generalize CPU init routine for the gcsu CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,03/32] riscv: Generalize CPU init routine for the base CPU [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,v2,02/32] sifive_e: Support the revB machine [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - - - --- 2020-06-19 Alistair Francis New
[PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register [PULL,v2,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,v2,00/32] riscv-to-apply queue - - - --- 2020-06-19 Alistair Francis New
[PULL,32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,28/32] target/riscv: Rename IBEX CPU init routine [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,25/32] hw/riscv: sifive_u: Add reset functionality [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,23/32] hw/riscv: sifive_u: Hook a GPIO controller [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,21/32] hw/riscv: sifive_gpio: Clean up the codes [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,20/32] hw/riscv: sifive_u: Generate device tree node for OTP [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,16/32] target/riscv: Use a smaller guess size for no-MMU PMP [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,15/32] riscv/opentitan: Connect the UART device [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,14/32] riscv/opentitan: Connect the PLIC device [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,13/32] hw/intc: Initial commit of lowRISC Ibex PLIC [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,12/32] hw/char: Initial commit of Ibex UART [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,11/32] riscv/opentitan: Fix the ROM size [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - - - --- 2020-06-19 Alistair Francis New
[PULL,10/32] target/riscv: Implement checks for hfence [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,09/32] target/riscv: Move the hfence instructions to the rvh decode [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,08/32] target/riscv: Report errors validating 2nd-stage PTEs [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,06/32] riscv: Keep the CPU init routine names consistent [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,05/32] riscv: Generalize CPU init routine for the imacu CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,04/32] riscv: Generalize CPU init routine for the gcsu CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,03/32] riscv: Generalize CPU init routine for the base CPU [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 1 - --- 2020-06-19 Alistair Francis New
[PULL,02/32] sifive_e: Support the revB machine [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - - - --- 2020-06-19 Alistair Francis New
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register - 2 - --- 2020-06-19 Alistair Francis New
[PULL,00/32] riscv-to-apply queue - - - --- 2020-06-19 Alistair Francis New
[v6,6/6] target/riscv: Use a smaller guess size for no-MMU PMP RISC-V Add the OpenTitan Machine - 1 - --- 2020-06-10 Alistair Francis New
[v6,5/6] riscv/opentitan: Connect the UART device RISC-V Add the OpenTitan Machine - 2 - --- 2020-06-10 Alistair Francis New
[v6,4/6] riscv/opentitan: Connect the PLIC device RISC-V Add the OpenTitan Machine - 2 - --- 2020-06-10 Alistair Francis New
[v6,3/6] hw/intc: Initial commit of lowRISC Ibex PLIC RISC-V Add the OpenTitan Machine - 1 - --- 2020-06-10 Alistair Francis New
[v6,2/6] hw/char: Initial commit of Ibex UART RISC-V Add the OpenTitan Machine - 1 - --- 2020-06-10 Alistair Francis New
[v6,1/6] riscv/opentitan: Fix the ROM size RISC-V Add the OpenTitan Machine - - - --- 2020-06-10 Alistair Francis New
[v2,17/17] target/riscv: Support the Virtual Instruction fault RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,16/17] target/riscv: Return the exception from invalid CSR accesses RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,14/17] target/riscv: Only support little endian guests RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,13/17] target/riscv: Only support a single VSXL length RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,11/17] target/riscv: Update the Hypervisor trap return/entry RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,10/17] target/riscv: Fix the interrupt cause code RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,09/17] target/riscv: Convert MSTATUS MTL to GVA RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,08/17] target/riscv: Don't allow guest to write to htinst RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,05/17] target/riscv: Allow setting a two-stage lookup in the virt status RISC-V: Update the Hypervisor spec to v0.6.1 - - - --- 2020-06-05 Alistair Francis New
[v2,04/17] target/riscv: Implement checks for hfence RISC-V: Update the Hypervisor spec to v0.6.1 - 1 - --- 2020-06-05 Alistair Francis New
[v2,03/17] target/riscv: Move the hfence instructions to the rvh decode RISC-V: Update the Hypervisor spec to v0.6.1 - 1 - --- 2020-06-05 Alistair Francis New
[v2,02/17] target/riscv: Report errors validating 2nd-stage PTEs RISC-V: Update the Hypervisor spec to v0.6.1 - 1 - --- 2020-06-05 Alistair Francis New
[v2,01/17] target/riscv: Set access as data_load when validating stage-2 PTEs RISC-V: Update the Hypervisor spec to v0.6.1 - 1 - --- 2020-06-05 Alistair Francis New
[PULL,09/15] riscv: sifive_e: Manually define the machine [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,08/15] docs: deprecated: Update the -bios documentation [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,07/15] target/riscv: Drop support for ISA spec version 1.09.1 [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,06/15] target/riscv: Remove the deprecated CPUs [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,05/15] hw/riscv: spike: Remove deprecated ISA specific machines [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 3 - --- 2020-06-03 Alistair Francis New
[PULL,04/15] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 2 - --- 2020-06-03 Alistair Francis New
[PULL,03/15] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 2 - --- 2020-06-03 Alistair Francis New
[PULL,02/15] riscv: Change the default behavior if no -bios option is specified [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() [PULL,01/15] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() - 1 - --- 2020-06-03 Alistair Francis New
[PULL,00/15] riscv-to-apply queue - - - --- 2020-06-03 Alistair Francis New
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