Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   1798 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,1/4] hw/riscv/sifive_u: Create a U54 SoC object - - - --- 2018-05-04 Alistair Francis New
[v1,2/4] hw/riscv/sifive_plic: Use gpios instead of irqs - - - --- 2018-05-04 Alistair Francis New
[v1,3/4] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - - - --- 2018-05-04 Alistair Francis New
[v1,4/4] hw/riscv/sifive_e: Create a E31 SoC object - - - --- 2018-05-04 Alistair Francis New
[v1,1/1] tests/docker: Add a Avocado Docker test - - - --- 2018-05-07 Alistair Francis New
[v2,1/7] hw/riscv/sifive_u: Create a U54 SoC object - 1 - --- 2018-05-11 Alistair Francis New
[v2,2/7] hw/riscv/sifive_e: Create a E31 SoC object - - - --- 2018-05-11 Alistair Francis New
[v2,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - - - --- 2018-05-11 Alistair Francis New
[v2,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - - - --- 2018-05-11 Alistair Francis New
[v2,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts - 1 - --- 2018-05-11 Alistair Francis New
[v2,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-05-11 Alistair Francis New
[v2,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-05-11 Alistair Francis New
[v3,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object - 1 - --- 2018-05-15 Alistair Francis New
[v3,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object - 1 - --- 2018-05-15 Alistair Francis New
[v3,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - 2 - --- 2018-05-15 Alistair Francis New
[v3,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - 1 - --- 2018-05-15 Alistair Francis New
[v3,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts - 1 - --- 2018-05-15 Alistair Francis New
[v3,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-05-15 Alistair Francis New
[v3,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-05-15 Alistair Francis New
[v2,1/1] tests/docker: Add a Avocado Docker test - 1 - --- 2018-05-18 Alistair Francis New
[v1,1/5] hw/riscv/virtio: Set the soc device tree node as a simple-bus - - - --- 2018-06-22 Alistair Francis New
[v1,2/5] hw/riscv/virt: Increase the number of interrupts - - - --- 2018-06-22 Alistair Francis New
[v1,3/5] hw/riscv/virt: Connect the Xilinx PCIe - - - --- 2018-06-22 Alistair Francis New
[v1,4/5] hw/riscv/virt: Connect a VGA PCIe device - - - --- 2018-06-22 Alistair Francis New
[v1,5/5] riscv64-softmmu.mak: Build Virtio Block support - - - --- 2018-06-22 Alistair Francis New
[PULL,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object - 1 - --- 2018-06-27 Alistair Francis New
[PULL,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object - 1 - --- 2018-06-27 Alistair Francis New
[PULL,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - 2 - --- 2018-06-27 Alistair Francis New
[PULL,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - 1 - --- 2018-06-27 Alistair Francis New
[PULL,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts - 1 - --- 2018-06-27 Alistair Francis New
[PULL,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-06-27 Alistair Francis New
[PULL,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-06-27 Alistair Francis New
[PULL,v2,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - 2 - --- 2018-06-29 Alistair Francis New
[PULL,v2,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v2,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-06-29 Alistair Francis New
[PULL,v3,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - 2 - --- 2018-07-03 Alistair Francis New
[PULL,v3,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v3,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-07-03 Alistair Francis New
[PULL,v4,1/7] hw/riscv/sifive_u: Create a SiFive U SoC object - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,2/7] hw/riscv/sifive_e: Create a SiFive E SoC object - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,3/7] hw/riscv/sifive_plic: Use gpios instead of irqs - 2 - --- 2018-07-06 Alistair Francis New
[PULL,v4,4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,5/7] hw/riscv/sifive_u: Set the interrupt controller number of interrupts - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ - 1 - --- 2018-07-06 Alistair Francis New
[PULL,v4,7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device - 1 - --- 2018-07-06 Alistair Francis New
[v2,1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus - - - --- 2018-07-10 Alistair Francis New
[v2,2/6] hw/riscv/virt: Increase the number of interrupts - - - --- 2018-07-10 Alistair Francis New
[v2,3/6] hw/riscv/virt: Connect the gpex PCIe - - - --- 2018-07-10 Alistair Francis New
[v2,4/6] hw/riscv/virt: Connect a VGA PCIe device - - - --- 2018-07-10 Alistair Francis New
[v2,5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe - - - --- 2018-07-10 Alistair Francis New
[v2,6/6] riscv64-softmmu.mak: Build Virtio Block support - - - --- 2018-07-10 Alistair Francis New
[v1,1/5] sifive_e: Fix crash when introspecting the device - 1 - --- 2018-07-17 Alistair Francis New
[v1,2/5] sifive_u: Fix crash when introspecting the device - 2 1 --- 2018-07-17 Alistair Francis New
[v1,3/5] virt: Fix crash when introspecting the device - 1 - --- 2018-07-17 Alistair Francis New
[v1,4/5] riscv_hart: Fix crash when introspecting the device - 1 - --- 2018-07-17 Alistair Francis New
[v1,5/5] spike: Fix crash when introspecting the device - 1 - --- 2018-07-17 Alistair Francis New
[PULL,1/5] sifive_e: Fix crash when introspecting the device - 2 1 --- 2018-07-18 Alistair Francis New
[PULL,2/5] sifive_u: Fix crash when introspecting the device - 2 1 --- 2018-07-18 Alistair Francis New
[PULL,3/5] virt: Fix crash when introspecting the device - 2 1 --- 2018-07-18 Alistair Francis New
[PULL,4/5] riscv_hart: Fix crash when introspecting the device - 2 1 --- 2018-07-18 Alistair Francis New
[PULL,5/5] spike: Fix crash when introspecting the device - 2 1 --- 2018-07-18 Alistair Francis New
[PULL,v2,for,3.0,1/5] sifive_e: Fix crash when introspecting the device - 3 1 --- 2018-07-19 Alistair Francis New
[PULL,v2,for,3.0,2/5] sifive_u: Fix crash when introspecting the device - 3 1 --- 2018-07-19 Alistair Francis New
[PULL,v2,for,3.0,3/5] virt: Fix crash when introspecting the device - 3 1 --- 2018-07-19 Alistair Francis New
[PULL,v2,for,3.0,4/5] riscv_hart: Fix crash when introspecting the device - 2 - --- 2018-07-19 Alistair Francis New
[PULL,v2,for,3.0,5/5] spike: Fix crash when introspecting the device - 2 - --- 2018-07-19 Alistair Francis New
[v1,1/4] target/riscv: Rename mbadaddr and sbadaddr RISC-V: Populate mtval and stval - - - --- 2018-07-25 Alistair Francis New
[v1,2/4] target/riscv: Implement the mtval illegal instruction RISC-V: Populate mtval and stval - - - --- 2018-07-25 Alistair Francis New
[v1,3/4] target/riscv: Implement the stval illegal instruction RISC-V: Populate mtval and stval - - - --- 2018-07-25 Alistair Francis New
[v1,4/4] target/riscv: set mtval and stval support RISC-V: Populate mtval and stval - - - --- 2018-07-25 Alistair Francis New
[v1,1/1] configure: Add RISC-V host support [v1,1/1] configure: Add RISC-V host support - 1 1 --- 2018-07-27 Alistair Francis New
[v3,1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Connect a PCIe host and graphics support to RISC-V - 1 - --- 2018-08-16 Alistair Francis New
[v3,2/6] hw/riscv/virt: Increase the number of interrupts Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-16 Alistair Francis New
[v3,3/6] hw/riscv/virt: Connect the gpex PCIe Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-16 Alistair Francis New
[v3,4/6] hw/riscv/virt: Connect a VGA PCIe device Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-16 Alistair Francis New
[v3,5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-16 Alistair Francis New
[v3,6/6] hw/riscv/virt: Connect a VirtIO net PCIe device Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-16 Alistair Francis New
[v4,1/7] hw/riscv/virtio: Set the soc device tree node as a simple-bus Connect a PCIe host and graphics support to RISC-V - 1 - --- 2018-08-29 Alistair Francis New
[v4,2/7] hw/riscv/spike: Set the soc device tree node as a simple-bus Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[v4,3/7] hw/riscv/virt: Increase the number of interrupts Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[v4,4/7] hw/riscv/virt: Connect the gpex PCIe Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[v4,5/7] riscv: Enable VGA and PCIE_VGA Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[v4,6/7] hw/riscv/sifive_u: Connect the Xilinx PCIe Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[v4,7/7] hw/riscv/virt: Connect a VirtIO net PCIe device Connect a PCIe host and graphics support to RISC-V - - - --- 2018-08-29 Alistair Francis New
[PULL,1/9] RISC-V: Update address bits to support sv39 and sv48 riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,2/9] RISC-V: Improve page table walker spec compliance riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,3/9] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,4/9] RISC-V: Simplify riscv_cpu_local_irqs_pending riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,5/9] target/riscv: optimize indirect branches riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,6/9] target/riscv: call gen_goto_tb on DISAS_TOO_MANY riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,7/9] hw/riscv/virtio: Set the soc device tree node as a simple-bus riscv-pullreq queue - 1 - --- 2018-09-04 Alistair Francis New
[PULL,8/9] hw/riscv/spike: Set the soc device tree node as a simple-bus riscv-pullreq queue - - - --- 2018-09-04 Alistair Francis New
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