Show patches with: Submitter = LIU Zhiwei       |   1061 patches
« 1 2 3 4 … 10 11 »
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISCV: support riscv vector extension 0.7.1 RISCV: support riscv vector extension 0.7.1 - - - --- 2019-08-28 LIU Zhiwei New
[v2,01/17] RISC-V: add vfp field in CPURISCVState RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,03/17] RISC-V: support vector extension csr RISC-V: support vector extension - 1 - --- 2019-09-11 LIU Zhiwei New
[v2,04/17] RISC-V: add vector extension configure instruction RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,05/17] RISC-V: add vector extension load and store instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,06/17] RISC-V: add vector extension fault-only-first implementation RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,07/17] RISC-V: add vector extension atomic instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,09/17] RISC-V: add vector extension integer instructions part2, bit/shift RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,11/17] RISC-V: add vector extension integer instructions part4, mul/div/merge RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,12/17] RISC-V: add vector extension fixed point instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,13/17] RISC-V: add vector extension float instruction part1, add/sub/mul/div RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,14/17] RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,15/17] RISC-V: add vector extension reduction instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,16/17] RISC-V: add vector extension mask instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v2,17/17] RISC-V: add vector extension premutation instructions RISC-V: support vector extension - - - --- 2019-09-11 LIU Zhiwei New
[v3,1/4] RISC-V: add vector extension field in CPURISCVState RISC-V: support vector extension part 1 - - - --- 2020-01-03 LIU Zhiwei New
[v3,2/4] RISC-V: configure and turn on vector extension from command line RISC-V: support vector extension part 1 - - - --- 2020-01-03 LIU Zhiwei New
[v3,3/4] RISC-V: support vector extension csr RISC-V: support vector extension part 1 - - - --- 2020-01-03 LIU Zhiwei New
[v3,4/4] RISC-V: add vector extension configure instruction RISC-V: support vector extension part 1 - - - --- 2020-01-03 LIU Zhiwei New
[1/3] select gdb fpu xml by single or double float extension [1/3] select gdb fpu xml by single or double float extension - - - --- 2020-01-10 LIU Zhiwei New
[2/3] RISC-V: use FIELD macro to define tb flags [1/3] select gdb fpu xml by single or double float extension - - - --- 2020-01-10 LIU Zhiwei New
[3/3] remove redundant check for fpu csr read and write interface [1/3] select gdb fpu xml by single or double float extension - 1 - --- 2020-01-10 LIU Zhiwei New
[v3,1/5] target/riscv: add vector unit stride load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-10 LIU Zhiwei New
[v3,2/5] target/riscv: add vector stride load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-10 LIU Zhiwei New
[v3,3/5] target/riscv: add vector index load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-10 LIU Zhiwei New
[v3,4/5] target/riscv: add fault-only-first unit stride load target/riscv: support vector extension part 2 - - - --- 2020-02-10 LIU Zhiwei New
[v3,5/5] target/riscv: add vector amo operations target/riscv: support vector extension part 2 - - - --- 2020-02-10 LIU Zhiwei New
[v4,1/4] target/riscv: add vector extension field in CPURISCVState target-riscv: support vector extension part 1 - 1 - --- 2020-02-10 LIU Zhiwei New
[v4,2/4] target/riscv: configure and turn on vector extension from command line target-riscv: support vector extension part 1 - 1 - --- 2020-02-10 LIU Zhiwei New
[v4,3/4] target/riscv: support vector extension csr target-riscv: support vector extension part 1 - - - --- 2020-02-10 LIU Zhiwei New
[v4,4/4] target/riscv: add vector configure instruction target-riscv: support vector extension part 1 - - - --- 2020-02-10 LIU Zhiwei New
[v5,1/4] target/riscv: add vector extension field in CPURISCVState target-riscv: support vector extension part 1 1 1 - --- 2020-02-21 LIU Zhiwei New
[v5,2/4] target/riscv: implementation-defined constant parameters target-riscv: support vector extension part 1 - 2 - --- 2020-02-21 LIU Zhiwei New
[v5,3/4] target/riscv: support vector extension csr target-riscv: support vector extension part 1 - - - --- 2020-02-21 LIU Zhiwei New
[v5,4/4] target/riscv: add vector configure instruction target-riscv: support vector extension part 1 - - - --- 2020-02-21 LIU Zhiwei New
[v4,1/5] target/riscv: add vector unit stride load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-25 LIU Zhiwei New
[v4,2/5] target/riscv: add vector stride load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-25 LIU Zhiwei New
[v4,3/5] target/riscv: add vector index load and store instructions target/riscv: support vector extension part 2 - - - --- 2020-02-25 LIU Zhiwei New
[v4,4/5] target/riscv: add fault-only-first unit stride load target/riscv: support vector extension part 2 - - - --- 2020-02-25 LIU Zhiwei New
[v4,5/5] target/riscv: add vector amo operations target/riscv: support vector extension part 2 - - - --- 2020-02-25 LIU Zhiwei New
[v3,1/1] target/riscv: add vector integer operations [v3,1/1] target/riscv: add vector integer operations - - - --- 2020-02-26 LIU Zhiwei New
[v6,1/4] target/riscv: add vector extension field in CPURISCVState target-riscv: support vector extension part 1 1 1 - --- 2020-02-29 LIU Zhiwei New
[v6,2/4] target/riscv: implementation-defined constant parameters target-riscv: support vector extension part 1 - 2 - --- 2020-02-29 LIU Zhiwei New
[v6,3/4] target/riscv: support vector extension csr target-riscv: support vector extension part 1 - - - --- 2020-02-29 LIU Zhiwei New
[v6,4/4] target/riscv: add vector configure instruction target-riscv: support vector extension part 1 - - - --- 2020-02-29 LIU Zhiwei New
[v3,01/60] target/riscv: add vector extension field in CPURISCVState target/riscv: support vector extension v0.7.1 1 1 - --- 2020-03-09 LIU Zhiwei New
[v3,02/60] target/riscv: implementation-defined constant parameters target/riscv: support vector extension v0.7.1 - 2 - --- 2020-03-09 LIU Zhiwei New
[v3,03/60] target/riscv: support vector extension csr target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,04/60] target/riscv: add vector configure instruction target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,05/60] target/riscv: add vector stride load and store instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,06/60] target/riscv: add vector index load and store instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,07/60] target/riscv: add fault-only-first unit stride load target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,08/60] target/riscv: add vector amo operations target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,09/60] target/riscv: vector single-width integer add and subtract target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,10/60] target/riscv: vector widening integer add and subtract target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,12/60] target/riscv: vector bitwise logical instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,13/60] target/riscv: vector single-width bit shift instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,14/60] target/riscv: vector narrowing integer right shift instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,15/60] target/riscv: vector integer comparison instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,17/60] target/riscv: vector single-width integer multiply instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,18/60] target/riscv: vector integer divide instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,19/60] target/riscv: vector widening integer multiply instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,20/60] target/riscv: vector single-width integer multiply-add instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,21/60] target/riscv: vector widening integer multiply-add instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,22/60] target/riscv: vector integer merge and move instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,23/60] target/riscv: vector single-width saturating add and subtract target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,24/60] target/riscv: vector single-width averaging add and subtract target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,25/60] target/riscv: vector single-width fractional multiply with rounding and saturation target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,26/60] target/riscv: vector widening saturating scaled multiply-add target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,27/60] target/riscv: vector single-width scaling shift instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,28/60] target/riscv: vector narrowing fixed-point clip instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,29/60] target/riscv: vector single-width floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,30/60] target/riscv: vector widening floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,31/60] target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,32/60] target/riscv: vector widening floating-point multiply target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,33/60] target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,34/60] target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,35/60] target/riscv: vector floating-point square-root instruction target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,36/60] target/riscv: vector floating-point min/max instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,37/60] target/riscv: vector floating-point sign-injection instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,38/60] target/riscv: vector floating-point compare instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,39/60] target/riscv: vector floating-point classify instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,40/60] target/riscv: vector floating-point merge instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,41/60] target/riscv: vector floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,42/60] target/riscv: widening floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,43/60] target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,45/60] target/riscv: vector wideing integer reduction instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,48/60] target/riscv: vector mask-register logical instructions target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,01/60] target/riscv: add vector extension field in CPURISCVState target/riscv: support vector extension v0.7.1 1 1 - --- 2020-03-09 LIU Zhiwei New
[v3,02/60] target/riscv: implementation-defined constant parameters target/riscv: support vector extension v0.7.1 - 2 - --- 2020-03-09 LIU Zhiwei New
[v3,03/60] target/riscv: support vector extension csr target/riscv: support vector extension v0.7.1 - - - --- 2020-03-09 LIU Zhiwei New
[v3,16/60] target/riscv: vector integer min/max instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - --- 2020-03-09 LIU Zhiwei New
[v3,44/60] target/riscv: vector single-width integer reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - --- 2020-03-09 LIU Zhiwei New
[v3,45/60] target/riscv: vector wideing integer reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - --- 2020-03-09 LIU Zhiwei New
[v3,46/60] target/riscv: vector single-width floating-point reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - --- 2020-03-09 LIU Zhiwei New
[v3,47/60] target/riscv: vector widening floating-point reduction instructions [v3,01/60] target/riscv: add vector extension field in CPURISCVState - - - --- 2020-03-09 LIU Zhiwei New
« 1 2 3 4 … 10 11 »