Show patches with: Submitter = Atish Patra       |    State = Action Required       |   304 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,2/2] target/riscv: Mask out upper sscofpmf bits during validation Minor mhpmevent related fixes 1 1 - --- 2025-02-06 Atish Patra New
[v2,1/2] target/riscv: Fix the hpmevent mask Minor mhpmevent related fixes 1 1 - --- 2025-02-06 Atish Patra New
[2/2] target/riscv: Mask out upper sscofpmf bits during validation Minor mhpmevent related fixes 1 1 - --- 2025-01-16 Atish Patra New
[1/2] target/riscv: Fix the hpmevent mask Minor mhpmevent related fixes - 1 - --- 2025-01-16 Atish Patra New
[v5,11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Patra New
[v5,10/11] target/riscv: Add implied rule for counter delegation extensions Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Patra New
[v5,09/11] target/riscv: Invoke pmu init after feature enable Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Patra New
[v5,08/11] target/riscv: Add counter delegation/configuration support Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Patra New
[v5,07/11] target/riscv: Add select value range check for counter delegation Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Patra New
[v5,06/11] target/riscv: Add counter delegation definitions Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Patra New
[v5,05/11] target/riscv: Add properties for counter delegation ISA extensions Add RISC-V Counter delegation ISA extension support - 2 - --- 2025-01-10 Atish Patra New
[v5,04/11] target/riscv: Support generic CSR indirect access Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Patra New
[v5,03/11] target/riscv: Enable S*stateen bits for AIA Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Patra New
[v5,02/11] target/riscv: Decouple AIA processing from xiselect and xireg Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Patra New
[v5,01/11] target/riscv: Add properties for Indirect CSR Access extension Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Patra New
[v4,11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-12-03 Atish Patra New
[v4,10/11] target/riscv: Add implied rule for counter delegation extensions Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-12-03 Atish Patra New
[v4,09/11] target/riscv: Invoke pmu init after feature enable Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-12-03 Atish Patra New
[v4,08/11] target/riscv: Add counter delegation/configuration support Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-12-03 Atish Patra New
[v4,07/11] target/riscv: Add select value range check for counter delegation Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-12-03 Atish Patra New
[v4,06/11] target/riscv: Add counter delegation definitions Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-12-03 Atish Patra New
[v4,05/11] target/riscv: Add properties for counter delegation ISA extensions Add RISC-V Counter delegation ISA extension support - 2 - --- 2024-12-03 Atish Patra New
[v4,04/11] target/riscv: Support generic CSR indirect access Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-12-03 Atish Patra New
[v4,03/11] target/riscv: Enable S*stateen bits for AIA Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-12-03 Atish Patra New
[v4,02/11] target/riscv: Decouple AIA processing from xiselect and xireg Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-12-03 Atish Patra New
[v4,01/11] target/riscv: Add properties for Indirect CSR Access extension Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-12-03 Atish Patra New
[v3,11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Add RISC-V Counter delegation ISA extension support 1 1 - --- 2024-11-18 Atish Patra New
[v3,10/11] target/riscv: Add implied rule for counter delegation extensions Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,09/11] target/riscv: Invoke pmu init after feature enable Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,08/11] target/riscv: Add counter delegation/configuration support Add RISC-V Counter delegation ISA extension support - - - --- 2024-11-18 Atish Patra New
[v3,07/11] target/riscv: Add select value range check for counter delegation Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,06/11] target/riscv: Add counter delegation definitions Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,05/11] target/riscv: Add properties for counter delegation ISA extensions Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,04/11] target/riscv: Support generic CSR indirect access Add RISC-V Counter delegation ISA extension support - - - --- 2024-11-18 Atish Patra New
[v3,03/11] target/riscv: Enable S*stateen bits for AIA Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,02/11] target/riscv: Decouple AIA processing from xiselect and xireg Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[v3,01/11] target/riscv: Add properties for Indirect CSR Access extension Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-11-18 Atish Patra New
[RFC,10/10] hw/riscv/virt.c: Generate the PMU node from the machine Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,09/10] target/riscv : Use the new tlb fill event functions Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,08/10] target/riscv: Update event mapping hashtable for invalid events Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,07/10] hw/riscv/virt.c : Disassociate virt PMU events Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,06/10] target/riscv: Define PMU event related structures Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,05/10] target/riscv: Rename the PMU events Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,04/10] target/riscv: Use uint64 instead of uint as key Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,03/10] target/riscv: Protect the hashtable modifications with a lock Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,02/10] target/riscv: Introduce helper functions for pmu hashtable lookup Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
[RFC,01/10] target/riscv: Fix the hpmevent mask Allow platform specific PMU event encoding - - - --- 2024-10-09 Atish Patra New
target/riscv: Add asserts for out-of-bound access target/riscv: Add asserts for out-of-bound access - 1 - --- 2024-07-24 Atish Patra New
[v2,13/13] target/riscv: Enable PMU related extensions to preferred rule Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,12/13] target/riscv: Add a preferred ISA extension rule Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,11/13] target/riscv: Repurpose the implied rule startergy Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,10/13] target/riscv: Enable sscofpmf for bare cpu by default Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,09/13] target/riscv: Invoke pmu init after feature enable Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-07-23 Atish Patra New
[v2,08/13] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Add RISC-V Counter delegation ISA extension support 1 - - --- 2024-07-23 Atish Patra New
[v2,07/13] target/riscv: Add counter delegation/configuration support Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,06/13] target/riscv: Add select value range check for counter delegation Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-07-23 Atish Patra New
[v2,05/13] target/riscv: Add counter delegation definitions Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-07-23 Atish Patra New
[v2,04/13] target/riscv: Support generic CSR indirect access Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v2,03/13] target/riscv: Enable S*stateen bits for AIA Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-07-23 Atish Patra New
[v2,02/13] target/riscv: Decouple AIA processing from xiselect and xireg Add RISC-V Counter delegation ISA extension support - 1 - --- 2024-07-23 Atish Patra New
[v2,01/13] target/riscv: Add properties for Indirect CSR Access extension Add RISC-V Counter delegation ISA extension support - - - --- 2024-07-23 Atish Patra New
[v8,13/13] target/riscv: Expose the Smcntrpmf config Add RISC-V ISA extension smcntrpmf support 1 - - --- 2024-07-11 Atish Patra New
[v8,12/13] target/riscv: Do not setup pmu timer if OF is disabled Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-07-11 Atish Patra New
[v8,11/13] target/riscv: More accurately model priv mode filtering. Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-07-11 Atish Patra New
[v8,10/13] target/riscv: Start counters from both mhpmcounter and mcountinhibit Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-07-11 Atish Patra New
[v8,09/13] target/riscv: Enforce WARL behavior for scounteren/hcounteren Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-07-11 Atish Patra New
[v8,08/13] target/riscv: Save counter values during countinhibit update Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-07-11 Atish Patra New
[v8,07/13] target/riscv: Implement privilege mode filtering for cycle/instret Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-07-11 Atish Patra New
[v8,06/13] target/riscv: Only set INH fields if priv mode is available Add RISC-V ISA extension smcntrpmf support 1 - - --- 2024-07-11 Atish Patra New
[v8,05/13] target/riscv: Add cycle & instret privilege mode filtering support Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-07-11 Atish Patra New
[v8,04/13] target/riscv: Add cycle & instret privilege mode filtering definitions Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-07-11 Atish Patra New
[v8,03/13] target/riscv: Add cycle & instret privilege mode filtering properties Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-07-11 Atish Patra New
[v8,02/13] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-07-11 Atish Patra New
[v8,01/13] target/riscv: Combine set_mode and set_virt functions. Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-07-11 Atish Patra New
[v7,11/11] target/riscv: Do not setup pmu timer if OF is disabled Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Patra New
[v7,10/11] target/riscv: More accurately model priv mode filtering. Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Patra New
[v7,09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Patra New
[v7,08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Patra New
[v7,07/11] target/riscv: Save counter values during countinhibit update Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-06-26 Atish Patra New
[v7,06/11] target/riscv: Implement privilege mode filtering for cycle/instret Add RISC-V ISA extension smcntrpmf support 1 1 - --- 2024-06-26 Atish Patra New
[v7,05/11] target/riscv: Add cycle & instret privilege mode filtering support Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Patra New
[v7,04/11] target/riscv: Add cycle & instret privilege mode filtering definitions Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Patra New
[v7,03/11] target/riscv: Add cycle & instret privilege mode filtering properties Add RISC-V ISA extension smcntrpmf support - 1 - --- 2024-06-26 Atish Patra New
[v7,02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Patra New
[v7,01/11] target/riscv: Combine set_mode and set_virt functions. Add RISC-V ISA extension smcntrpmf support - 2 - --- 2024-06-26 Atish Patra New
[3/3] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Assorted fixes for PMU - 2 - --- 2024-04-29 Atish Patra New
[2/3] target/riscv: Enforce WARL behavior for scounteren/hcounteren Assorted fixes for PMU - 2 - --- 2024-04-29 Atish Patra New
[1/3] target/riscv: Save counter values during countinhibit update Assorted fixes for PMU - 1 - --- 2024-04-29 Atish Patra New
[v5,5/5] target/riscv: Implement privilege mode filtering for cycle/instret Add ISA extension smcntrpmf support - 1 - --- 2024-02-28 Atish Patra New
[v5,4/5] target/riscv: Add cycle & instret privilege mode filtering support Add ISA extension smcntrpmf support - 1 - --- 2024-02-28 Atish Patra New
[v5,3/5] target/riscv: Add cycle & instret privilege mode filtering definitions Add ISA extension smcntrpmf support - 1 - --- 2024-02-28 Atish Patra New
[v5,2/5] target/riscv: Add cycle & instret privilege mode filtering properties Add ISA extension smcntrpmf support - 1 - --- 2024-02-28 Atish Patra New
[v5,1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Add ISA extension smcntrpmf support - 3 - --- 2024-02-28 Atish Patra New
[RFC,8/8] target/riscv: Add counter delegation/configuration support Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,7/8] target/riscv: Add select value range check for counter delegation Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,6/8] target/riscv: Add counter delegation definitions Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,5/8] target/riscv: Add smcdeleg/ssccfg properties Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,4/8] target/riscv: Support generic CSR indirect access Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,3/8] target/riscv: Enable S*stateen bits for AIA Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
[RFC,2/8] target/riscv: Decouple AIA processing from xiselect and xireg Add Counter delegation ISA extension support - - - --- 2024-02-17 Atish Patra New
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