From patchwork Thu Nov 3 23:35:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Evans X-Patchwork-Id: 9411697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4563860234 for ; Fri, 4 Nov 2016 00:54:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 377722B02F for ; Fri, 4 Nov 2016 00:54:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C6AE2B036; Fri, 4 Nov 2016 00:54:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AC6D72B02F for ; Fri, 4 Nov 2016 00:54:57 +0000 (UTC) Received: from localhost ([::1]:35833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2SmX-0005Si-1x for patchwork-qemu-devel@patchwork.kernel.org; Thu, 03 Nov 2016 20:54:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <3xMkbWAMKCo0u0vx55x2v.t537v3B-uvCv2454x4B.58x@flex--dje.bounces.google.com>) id 1c2RXj-0007oO-0b for qemu-devel@nongnu.org; Thu, 03 Nov 2016 19:35:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <3xMkbWAMKCo0u0vx55x2v.t537v3B-uvCv2454x4B.58x@flex--dje.bounces.google.com>) id 1c2RXh-00067H-Rk for qemu-devel@nongnu.org; Thu, 03 Nov 2016 19:35:35 -0400 Received: from mail-pa0-x24a.google.com ([2607:f8b0:400e:c03::24a]:34476) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from <3xMkbWAMKCo0u0vx55x2v.t537v3B-uvCv2454x4B.58x@flex--dje.bounces.google.com>) id 1c2RXh-00066N-LD for qemu-devel@nongnu.org; Thu, 03 Nov 2016 19:35:33 -0400 Received: by mail-pa0-x24a.google.com with SMTP id yw6so2035761pac.1 for ; Thu, 03 Nov 2016 16:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:message-id:date:subject:from:to; bh=OuiSxgVlf2REyqvc3D2Gvmgrc1BBpmoLlo+tjTbAL80=; b=KZZMOWzEiFAIJDtWV+Khcql0SLUaep7mgfTLN0tgmiqafO3jlj3atgOgGDvSVoHHSS 7d6GWUafAYsSf9Y3CR5NZiZxFMbOfT9i3GCBZPN0u0GElkJxu0PJOM2flc/Ursdopi0d Rne5+8lTMjF0Mdm/SsbyAx1NDkcs0jZHpp0BMNfk+BchIENQ8MMXuzQayZh8FRoSVMO3 WXAAbpPnSkkz2RgWz35tOM1NaJH+jZ4AtOnhvs8A0srDcx9xVDqLpgbCkzY5S5yDewSw bqb626YL1+l6e1Dcr3jRM07wDna6QhFXx/DbJXOkQAIxcxQMRMjgkalKENTlsedYgsUq eNLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:message-id:date:subject:from:to; bh=OuiSxgVlf2REyqvc3D2Gvmgrc1BBpmoLlo+tjTbAL80=; b=Bn5urOkWIGqrOdqUz7Nb99K18idg5mfKoTk3UYzyCWtd6d/v2MYiORZG15It4hB/Gy lT/wMIBmyLP8I1nEYSNT2TPlT+fl/H51A6vzCIai3WICs9qht3I4ZZL65JC4Lj4XxhY+ pEWF/Wd6mDkv3xUY8KnyZC0H6j3m+CkJ4fN3iATiSOnfcfC9NKPnh8AjW8GeoKH7tEIe eYskAw45MSaIY1iveJ68TAqvOWVDxRgc5FgZX3NpocLhmYpqfw6BkiZoW38zfmyUmq6J 5hofyzTBAKdf3WZsgfeVOGt9zY55uAfQAqyN9y9AEJq63rF5xO9CkKwPyxigZke5QalE wBEA== X-Gm-Message-State: ABUngvfwVAp9OwoGOKlGv+E1rEgKqW/18FvXB/u9AVsxqUYiiD28DaZGJAP+7jjvHh0lCB6lJ4UW9X5unRx8OMrY0rN0eliBN1P40qbGh84ukU4y6OI8ELqxQriKLi+g5/LrCwmVVNt4M+l9qRjMIuPWZVmKMSOAbBACK843UkoLCZ0= MIME-Version: 1.0 X-Received: by 10.98.111.2 with SMTP id k2mr3308039pfc.42.1478216132074; Thu, 03 Nov 2016 16:35:32 -0700 (PDT) Message-ID: <001a113dca8274572005406e03c3@google.com> Date: Thu, 03 Nov 2016 23:35:32 +0000 From: Doug Evans To: qemu-devel@nongnu.org, pbonzini@redhat.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c03::24a X-Mailman-Approved-At: Thu, 03 Nov 2016 20:51:38 -0400 Subject: [Qemu-devel] [PATCH] x86: Fix x86_64 'g' packet response to gdb from 32-bit mode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The remote protocol can't handle flipping back and forth between 32-bit and 64-bit regs. To compensate, pretend "as if" on 64-bit cpu when in 32-bit mode. Signed-off-by: Doug Evans Reviewed-by: Richard Henderson --- target-i386/gdbstub.c | 52 ++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 13 deletions(-) } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { @@ -60,8 +72,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || - (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { + if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) { stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0)); stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1)); return 16; @@ -69,8 +80,12 @@ int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) } else { switch (n) { case IDX_IP_REG: - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - return gdb_get_reg64(mem_buf, env->eip); + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, env->eip); + } else { + return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL); + } } else { return gdb_get_reg32(mem_buf, env->eip); } @@ -151,9 +166,17 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUX86State *env = &cpu->env; uint32_t tmp; + /* N.B. GDB can't deal with changes in registers or sizes in the middle + of a session. So if we're in 32-bit mode on a 64-bit cpu, still act + as if we're on a 64-bit cpu. */ + if (n < CPU_NB_REGS) { - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - env->regs[gpr_map[n]] = ldtul_p(mem_buf); + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + env->regs[gpr_map[n]] = ldtul_p(mem_buf); + } else if (n < CPU_NB_REGS32) { + env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL; + } return sizeof(target_ulong); } else if (n < CPU_NB_REGS32) { n = gpr_map32[n]; @@ -169,8 +192,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; - if (n < CPU_NB_REGS32 || - (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { + if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) { env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf); env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8); return 16; @@ -178,8 +200,12 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else { switch (n) { case IDX_IP_REG: - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - env->eip = ldq_p(mem_buf); + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + env->eip = ldq_p(mem_buf); + } else { + env->eip = ldq_p(mem_buf) & 0xffffffffUL; + } return 8; } else { env->eip &= ~0xffffffffUL; -- diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c index c494535..9b94ab8 100644 --- a/target-i386/gdbstub.c +++ b/target-i386/gdbstub.c @@ -44,10 +44,22 @@ int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + /* N.B. GDB can't deal with changes in registers or sizes in the middle + of a session. So if we're in 32-bit mode on a 64-bit cpu, still act + as if we're on a 64-bit cpu. */ + if (n < CPU_NB_REGS) { - if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { - return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); - } else if (n < CPU_NB_REGS32) { + if (TARGET_LONG_BITS == 64) { + if (env->hflags & HF_CS64_MASK) { + return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); + } else if (n < CPU_NB_REGS32) { + return gdb_get_reg64(mem_buf, + env->regs[gpr_map[n]] & 0xffffffffUL); + } else { + memset(mem_buf, 0, sizeof(target_ulong)); + return sizeof(target_ulong); + } + } else { return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); }