From patchwork Wed Oct 27 13:46:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 12587509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C267C433F5 for ; Wed, 27 Oct 2021 14:57:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F25B60724 for ; Wed, 27 Oct 2021 14:57:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2F25B60724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=eik.bme.hu Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:37074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mfkMQ-0000Wc-Ao for qemu-devel@archiver.kernel.org; Wed, 27 Oct 2021 10:57:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfjS5-0003tn-Dm for qemu-devel@nongnu.org; Wed, 27 Oct 2021 09:58:50 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28118) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mfjS0-0004Tv-LQ for qemu-devel@nongnu.org; Wed, 27 Oct 2021 09:58:47 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id E0BDA75619D; Wed, 27 Oct 2021 15:58:41 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id A68C175603A; Wed, 27 Oct 2021 15:58:41 +0200 (CEST) Message-Id: <029a0597b27a0f2ed989f5838451269c176b6310.1635342377.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 05/11] hw/char/sh_serial: Rename type sh_serial_state to SHSerialState Date: Wed, 27 Oct 2021 15:46:17 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Magnus Damm , Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coding style says types should be camel case. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index bbf7586892..6d02e0ad11 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -73,9 +73,9 @@ typedef struct { qemu_irq txi; qemu_irq tei; qemu_irq bri; -} sh_serial_state; +} SHSerialState; -static void sh_serial_clear_fifo(sh_serial_state *s) +static void sh_serial_clear_fifo(SHSerialState *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); s->rx_cnt = 0; @@ -86,7 +86,7 @@ static void sh_serial_clear_fifo(sh_serial_state *s) static void sh_serial_write(void *opaque, hwaddr offs, uint64_t val, unsigned size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; unsigned char ch; trace_sh_serial_write(size, offs, val); @@ -205,7 +205,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, static uint64_t sh_serial_read(void *opaque, hwaddr offs, unsigned size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; uint32_t ret = ~0; #if 0 @@ -309,12 +309,12 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, return ret; } -static int sh_serial_can_receive(sh_serial_state *s) +static int sh_serial_can_receive(SHSerialState *s) { return s->scr & (1 << 4); } -static void sh_serial_receive_break(sh_serial_state *s) +static void sh_serial_receive_break(SHSerialState *s) { if (s->feat & SH_SERIAL_FEAT_SCIF) { s->sr |= (1 << 4); @@ -323,13 +323,13 @@ static void sh_serial_receive_break(sh_serial_state *s) static int sh_serial_can_receive1(void *opaque) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; return sh_serial_can_receive(s); } static void sh_serial_timeout_int(void *opaque) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; s->flags |= SH_SERIAL_FLAG_RDF; if (s->scr & (1 << 6) && s->rxi) { @@ -339,7 +339,7 @@ static void sh_serial_timeout_int(void *opaque) static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; if (s->feat & SH_SERIAL_FEAT_SCIF) { int i; @@ -369,7 +369,7 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) static void sh_serial_event(void *opaque, QEMUChrEvent event) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; if (event == CHR_EVENT_BREAK) { sh_serial_receive_break(s); } @@ -390,9 +390,7 @@ void sh_serial_init(MemoryRegion *sysmem, qemu_irq tei_source, qemu_irq bri_source) { - sh_serial_state *s; - - s = g_malloc0(sizeof(sh_serial_state)); + SHSerialState *s = g_malloc0(sizeof(*s)); s->feat = feat; s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;