From patchwork Tue Feb 7 02:56:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Bobroff X-Patchwork-Id: 9559145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A76E7602B1 for ; Tue, 7 Feb 2017 03:06:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B6E92624A for ; Tue, 7 Feb 2017 03:06:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 904BF212E8; Tue, 7 Feb 2017 03:06:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C15D4212E8 for ; Tue, 7 Feb 2017 03:06:41 +0000 (UTC) Received: from localhost ([::1]:51753 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1caw76-0003Hl-RI for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Feb 2017 22:06:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cavz6-0005PD-MT for qemu-devel@nongnu.org; Mon, 06 Feb 2017 21:58:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cavz3-0002yP-Gx for qemu-devel@nongnu.org; Mon, 06 Feb 2017 21:58:24 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:57489) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cavz3-0002xE-8T for qemu-devel@nongnu.org; Mon, 06 Feb 2017 21:58:21 -0500 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v172s1BV061678 for ; Mon, 6 Feb 2017 21:58:20 -0500 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 28f4px28p0-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 06 Feb 2017 21:58:19 -0500 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 7 Feb 2017 12:58:15 +1000 Received: from d23relay10.au.ibm.com (d23relay10.au.ibm.com [9.190.26.77]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 193312CE8057; Tue, 7 Feb 2017 13:58:15 +1100 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v172w7JU31850510; Tue, 7 Feb 2017 13:58:15 +1100 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v172vgYd004395; Tue, 7 Feb 2017 13:57:43 +1100 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v172vf8E003510; Tue, 7 Feb 2017 13:57:42 +1100 Received: from tungsten.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 0CD0CA03B1; Tue, 7 Feb 2017 13:56:53 +1100 (AEDT) From: Sam Bobroff To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 13:56:52 +1100 X-Mailer: git-send-email 2.1.4 In-Reply-To: References: In-Reply-To: References: X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17020702-0004-0000-0000-000001DD9209 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17020702-0005-0000-0000-0000099EC63A Message-Id: <02c42ec7c0d07633c974e2ecd30054cc82e3d1c6.1486436186.git.sam.bobroff@au1.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-07_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702070026 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [RFC PATCH 9/9] spapr: Small cleanup of PPC MMU enums X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The PPC MMU types are sometimes treated as if they were a bit field and sometime as if they were an enum which causes maintenance problems: flipping bits in the MMU type (which is done on both the 1TB segment and 64K segment bits) currently produces new MMU type values that are not handled in every "switch" on it, sometimes causing an abort(). This patch provides some macros that can be used to filter out the "bit field-like" bits so that the remainder of the value can be switched on, like an enum. This allows removal of all of the "degraded" types from the list and should ease maintenance. Signed-off-by: Sam Bobroff Reviewed-by: David Gibson --- hw/ppc/spapr.c | 10 +++----- target/ppc/cpu-qom.h | 12 ++++----- target/ppc/kvm.c | 8 +++--- target/ppc/mmu-hash64.c | 10 ++++---- target/ppc/mmu_helper.c | 67 ++++++++++++++++++++----------------------------- target/ppc/translate.c | 12 ++++----- 6 files changed, 51 insertions(+), 68 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 325a9c587b..f9de02759a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -222,18 +222,16 @@ static int spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, uint8_t *pa_features; size_t pa_size; - switch (env->mmu_model) { - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_2_06: pa_features = pa_features_206; pa_size = sizeof(pa_features_206); break; - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_2_07: pa_features = pa_features_207; pa_size = sizeof(pa_features_207); break; - case POWERPC_MMU_3_00: + case POWERPC_MMU_VER_3_00: pa_features = pa_features_300; pa_size = sizeof(pa_features_300); break; diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 1577cc8224..8ea055c18d 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -79,21 +79,21 @@ enum powerpc_mmu_t { POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000003, - /* Architecture 2.06 "degraded" (no 1T segments) */ - POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* Architecture 2.07 "degraded" (no 1T segments) */ - POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR - | 0x00000004, /* Architecture 3.00 variant */ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000005, }; +#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) +#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) +#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) +#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) +#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) +#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) /*****************************************************************************/ /* Exception model */ diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 0d1443616c..1687d8e47e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -285,8 +285,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, info->flags |= KVM_PPC_1T_SEGMENTS; } - if (env->mmu_model == POWERPC_MMU_2_06 || - env->mmu_model == POWERPC_MMU_2_07) { + if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 || + POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) { info->slb_size = 32; } else { info->slb_size = 64; @@ -300,8 +300,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, i++; /* 64K on MMU 2.06 and later */ - if (env->mmu_model == POWERPC_MMU_2_06 || - env->mmu_model == POWERPC_MMU_2_07) { + if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 || + POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) { info->sps[i].page_shift = 16; info->sps[i].slb_enc = 0x110; info->sps[i].enc[0].page_shift = 16; diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0efc8c63fa..7f0b7b3df5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1004,8 +1004,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val) uint64_t lpcr = 0; /* Filter out bits */ - switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ + switch (POWERPC_MMU_VER(env->mmu_model)) { + case POWERPC_MMU_VER_64B: /* 970 */ if (val & 0x40) { lpcr |= LPCR_LPES0; } @@ -1031,19 +1031,19 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val) * to dig HRMOR out of HID5 */ break; - case POWERPC_MMU_2_03: /* P5p */ + case POWERPC_MMU_VER_2_03: /* P5p */ lpcr = val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | LPCR_RMI | LPCR_HDICE); break; - case POWERPC_MMU_2_06: /* P7 */ + case POWERPC_MMU_VER_2_06: /* P7 */ lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); break; - case POWERPC_MMU_2_07: /* P8 */ + case POWERPC_MMU_VER_2_07: /* P8 */ lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 172a305e0f..e65e4d337f 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1260,7 +1260,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf, void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) { - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { case POWERPC_MMU_BOOKE: mmubooke_dump_mmu(f, cpu_fprintf, env); break; @@ -1272,12 +1272,10 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) mmu6xx_dump_mmu(f, cpu_fprintf, env); break; #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); break; #endif @@ -1412,14 +1410,12 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) CPUPPCState *env = &cpu->env; mmu_ctx_t ctx; - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: return ppc_hash64_get_phys_page_debug(cpu, addr); #endif @@ -1904,6 +1900,12 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) { PowerPCCPU *cpu = ppc_env_get_cpu(env); +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) { + env->tlb_need_flush = 0; + tlb_flush(CPU(cpu)); + } else +#endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1928,21 +1930,12 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) break; case POWERPC_MMU_32B: case POWERPC_MMU_601: -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: - case POWERPC_MMU_3_00: -#endif /* defined(TARGET_PPC64) */ env->tlb_need_flush = 0; tlb_flush(CPU(cpu)); break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model); + cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model); break; } } @@ -1951,6 +1944,16 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) addr &= TARGET_PAGE_MASK; +#if defined(TARGET_PPC64) + if (env->mmu_model & POWERPC_MMU_64) { + /* tlbie invalidate TLBs for all segments */ + /* XXX: given the fact that there are too many segments to invalidate, + * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, + * we just invalidate all TLBs + */ + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; + } else +#endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1968,22 +1971,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) */ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; break; -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: - case POWERPC_MMU_3_00: - /* tlbie invalidate TLBs for all segments */ - /* XXX: given the fact that there are too many segments to invalidate, - * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, - * we just invalidate all TLBs - */ - env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; - break; -#endif /* defined(TARGET_PPC64) */ default: /* Should never reach here with other MMU models */ assert(0); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 121218087f..1edf3f2133 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6910,18 +6910,16 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } #endif - switch (env->mmu_model) { + switch (POWERPC_MMU_VER(env->mmu_model)) { case POWERPC_MMU_32B: case POWERPC_MMU_601: case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_03: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06a: - case POWERPC_MMU_2_07: - case POWERPC_MMU_2_07a: + case POWERPC_MMU_VER_64B: + case POWERPC_MMU_VER_2_03: + case POWERPC_MMU_VER_2_06: + case POWERPC_MMU_VER_2_07: #endif cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],