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Mon, 25 Mar 2019 12:02:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511750; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DCYeiaZ7Txq3XDAmFnR36pIeypmNDiDxPYYOvhv438a42zSd5eZyz0glG9AePRVs3 GcBTQWWK6pQa5liMoSfC//ARoJma/8WLy8m89wm8noOCRkanDA5BSK5NSG32HGsclg fdTZAYC+E4od48qMSakc3XqykkOJhI4o1+gavKYE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:57 +0100 Message-Id: <052e5afb8c6cbaf6fac894ee7bfdc7ed03d38788.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Split the existing reset procedure into 3 phases. Test the resetting flag to discard register accesses and character reception. Also adds a active high reset io. Signed-off-by: Damien Hedde --- hw/char/cadence_uart.c | 48 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fbdbd463bb..694c8ea614 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -222,6 +222,10 @@ static int uart_can_receive(void *opaque) int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (qdev_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); } @@ -337,6 +341,10 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) CadenceUARTState *s = opaque; uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -350,6 +358,10 @@ static void uart_event(void *opaque, int event) CadenceUARTState *s = opaque; uint8_t buf = '\0'; + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (event == CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -382,6 +394,10 @@ static void uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s = opaque; + if (qdev_is_resetting((DeviceState *)opaque)) { + return; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { @@ -440,6 +456,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset, CadenceUARTState *s = opaque; uint32_t c = 0; + if (qdev_is_resetting((DeviceState *)opaque)) { + return 0; + } + offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { c = 0; @@ -459,9 +479,9 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, bool cold) { - CadenceUARTState *s = CADENCE_UART(dev); + CadenceUARTState *s = CADENCE_UART(obj); s->r[R_CR] = 0x00000128; s->r[R_IMR] = 0; @@ -470,6 +490,18 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] = 0x0000028B; s->r[R_BDIV] = 0x0000000F; s->r[R_TTRIG] = 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); + + qemu_set_irq(s->irq, 0); +} + +static void cadence_uart_reset_exit(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); uart_rx_reset(s); uart_tx_reset(s); @@ -498,6 +530,8 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; + + qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_ACTIVE_HIGH); } static int cadence_uart_post_load(void *opaque, int version_id) @@ -532,6 +566,10 @@ static const VMStateDescription vmstate_cadence_uart = { VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &device_vmstate_reset, + NULL } }; @@ -546,9 +584,11 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data) dc->realize = cadence_uart_realize; dc->vmsd = &vmstate_cadence_uart; - dc->reset = cadence_uart_reset; + dc->reset_phases.init = cadence_uart_reset_init; + dc->reset_phases.hold = cadence_uart_reset_hold; + dc->reset_phases.exit = cadence_uart_reset_exit; dc->props = cadence_uart_properties; - } +} static const TypeInfo cadence_uart_info = { .name = TYPE_CADENCE_UART,