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[109.242.226.170]) by smtp.gmail.com with ESMTPSA id v10-20020a5d678a000000b0032d9f32b96csm569185wru.62.2023.10.13.01.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:47:33 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Andrew Jeffery , Joel Stanley , Yoshinori Sato , Magnus Damm , qemu-arm@nongnu.org (open list:ARM cores) Subject: [RFC PATCH v3 11/78] hw/timer: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 11:45:39 +0300 Message-Id: <089c04aaa8a001c7af0e44c309122c738ff2bf50.1697186560.git.manos.pitsidianakis@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- hw/timer/a9gtimer.c | 8 ++-- hw/timer/aspeed_timer.c | 1 + hw/timer/pxa2xx_timer.c | 94 ++++++++++++++++++++--------------------- hw/timer/renesas_tmr.c | 2 +- hw/timer/sh_timer.c | 8 ++-- 5 files changed, 57 insertions(+), 56 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 5e959b6d09..b83d51da96 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -143,7 +143,7 @@ static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size) switch (addr) { case R_COUNTER_HI: shift = 32; - /* fallthrough */ + fallthrough; case R_COUNTER_LO: update = a9_gtimer_get_update(s); ret = extract64(update.new, shift, 32); @@ -156,7 +156,7 @@ static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size) break; case R_COMPARATOR_HI: shift = 32; - /* fallthrough */ + fallthrough; case R_COMPARATOR_LO: ret = extract64(gtb->compare, shift, 32); break; @@ -185,7 +185,7 @@ static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value, switch (addr) { case R_COUNTER_HI: shift = 32; - /* fallthrough */ + fallthrough; case R_COUNTER_LO: /* * Keep it simple - ARM docco explicitly says to disable timer before @@ -209,7 +209,7 @@ static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value, break; case R_COMPARATOR_HI: shift = 32; - /* fallthrough */ + fallthrough; case R_COMPARATOR_LO: a9_gtimer_update(s, false); gtb->compare = deposit64(gtb->compare, shift, 32, value); diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 72161f07bb..b343b7ab2c 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -284,6 +284,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, break; } /* fall through to re-enable */ + fallthrough; case TIMER_REG_STATUS: if (timer_enabled(t)) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index 2ae5ae3212..11863e1a42 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -167,27 +167,27 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, switch (offset) { case OSMR3: tm ++; - /* fall through */ + fallthrough; case OSMR2: tm ++; - /* fall through */ + fallthrough; case OSMR1: tm ++; - /* fall through */ + fallthrough; case OSMR0: return s->timer[tm].value; case OSMR11: tm ++; - /* fall through */ + fallthrough; case OSMR10: tm ++; - /* fall through */ + fallthrough; case OSMR9: tm ++; - /* fall through */ + fallthrough; case OSMR8: tm ++; - /* fall through */ + fallthrough; case OSMR7: tm ++; - /* fall through */ + fallthrough; case OSMR6: tm ++; - /* fall through */ + fallthrough; case OSMR5: tm ++; - /* fall through */ + fallthrough; case OSMR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -196,19 +196,19 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->lastload, s->freq, NANOSECONDS_PER_SECOND); case OSCR11: tm ++; - /* fall through */ + fallthrough; case OSCR10: tm ++; - /* fall through */ + fallthrough; case OSCR9: tm ++; - /* fall through */ + fallthrough; case OSCR8: tm ++; - /* fall through */ + fallthrough; case OSCR7: tm ++; - /* fall through */ + fallthrough; case OSCR6: tm ++; - /* fall through */ + fallthrough; case OSCR5: tm ++; - /* fall through */ + fallthrough; case OSCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -236,19 +236,19 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, case OWER: return s->reset3; case OMCR11: tm ++; - /* fall through */ + fallthrough; case OMCR10: tm ++; - /* fall through */ + fallthrough; case OMCR9: tm ++; - /* fall through */ + fallthrough; case OMCR8: tm ++; - /* fall through */ + fallthrough; case OMCR7: tm ++; - /* fall through */ + fallthrough; case OMCR6: tm ++; - /* fall through */ + fallthrough; case OMCR5: tm ++; - /* fall through */ + fallthrough; case OMCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -277,29 +277,29 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, switch (offset) { case OSMR3: tm ++; - /* fall through */ + fallthrough; case OSMR2: tm ++; - /* fall through */ + fallthrough; case OSMR1: tm ++; - /* fall through */ + fallthrough; case OSMR0: s->timer[tm].value = value; pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; case OSMR11: tm ++; - /* fall through */ + fallthrough; case OSMR10: tm ++; - /* fall through */ + fallthrough; case OSMR9: tm ++; - /* fall through */ + fallthrough; case OSMR8: tm ++; - /* fall through */ + fallthrough; case OSMR7: tm ++; - /* fall through */ + fallthrough; case OSMR6: tm ++; - /* fall through */ + fallthrough; case OSMR5: tm ++; - /* fall through */ + fallthrough; case OSMR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -313,19 +313,19 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, pxa2xx_timer_update(s, s->lastload); break; case OSCR11: tm ++; - /* fall through */ + fallthrough; case OSCR10: tm ++; - /* fall through */ + fallthrough; case OSCR9: tm ++; - /* fall through */ + fallthrough; case OSCR8: tm ++; - /* fall through */ + fallthrough; case OSCR7: tm ++; - /* fall through */ + fallthrough; case OSCR6: tm ++; - /* fall through */ + fallthrough; case OSCR5: tm ++; - /* fall through */ + fallthrough; case OSCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -350,11 +350,11 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, s->reset3 = value; break; case OMCR7: tm ++; - /* fall through */ + fallthrough; case OMCR6: tm ++; - /* fall through */ + fallthrough; case OMCR5: tm ++; - /* fall through */ + fallthrough; case OMCR4: if (!pxa2xx_timer_has_tm4(s)) goto badreg; @@ -368,11 +368,11 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, } break; case OMCR11: tm ++; - /* fall through */ + fallthrough; case OMCR10: tm ++; - /* fall through */ + fallthrough; case OMCR9: tm ++; - /* fall through */ + fallthrough; case OMCR8: tm += 4; if (!pxa2xx_timer_has_tm4(s)) goto badreg; diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c index 43b31213bc..a32521e3c3 100644 --- a/hw/timer/renesas_tmr.c +++ b/hw/timer/renesas_tmr.c @@ -236,7 +236,7 @@ static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size) } else if (ch == 0) { return concat_reg(tmr->tcora); } - /* fall through */ + fallthrough; case A_TCORB: if (size == 1) { return tmr->tcorb[ch]; diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 7788939766..6dbfc2595b 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -131,7 +131,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) if (s->feat & TIMER_FEAT_EXTCLK) { break; } - /* fallthrough */ + fallthrough; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Reserved TPSC value\n", __func__); @@ -145,7 +145,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) if (s->feat & TIMER_FEAT_EXTCLK) { break; } - /* fallthrough */ + fallthrough; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Reserved CKEG value\n", __func__); @@ -158,7 +158,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) if (s->feat & TIMER_FEAT_CAPT) { break; } - /* fallthrough */ + fallthrough; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Reserved ICPE value\n", __func__); @@ -194,7 +194,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) s->tcpr = value; break; } - /* fallthrough */ + fallthrough; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);