| Message ID | 107c154303a7f08c452199df250c274f40d274ec.1525464177.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, May 5, 2018 at 8:12 AM, Alistair Francis <alistair.francis@wdc.com> wrote: > Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. > > We leave the SoC, RAM, device tree and reset/fdt loading as part of the > machine. All the other device creation has been moved to the SoC. > There is a tiny problem that we will have to resolve with renaming, otherwise we will end up with lots of SOCs that are the essentially same with a different CPU. There is an intention to add a HiFive1 and HiFiveU board in the future however we were very explicit in renaming sifive_e300 and sifive_u500 to sifive_e and sifive_u. If you read the code more closely you'll notice that we instantiate the sifive_u board with a U34 if 32-bit and a U54 if 64-bit. #if defined(TARGET_RISCV32) #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 #elif defined(TARGET_RISCV64) #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 #endif The rationale is that sifive_e and sifive_u can eventually be customized to represent different configurations of SiFive Core IP. We won't want to end up hardcoding specific models in sifive_e or sifive_u SiFive have been talking internally about having sifive_e and sifive_u reconfigurable, possibly even to the extend where we can configure with a memory map. This is somewhat consistent with what SiFive do internally as the FE310 and FU540 are configurations generated by a core generator. Now comes the question of whether its the right time to add a 'hifive1' or 'hifiveu' machine. I don't think it is immediately necessary. The thought being that we would be able to give a configuration string of file to sifive_u e.g. "e51,u54,u54,u54". There is a different between the U54 and the U54-MC which has an E51 core for management tasks. The PLIC has already been written with this in mind, and is re-configurable to support the U54-MC memory layout. In anycase. The change is simply to use sifive_u_soc or sifive_u without the 54 (given it configures with a U34 in 32-bit like the sifive_e configures with an E51 in 64-bit mode, both valid configurations) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_u.c | 90 ++++++++++++++++++++++++++++--------- > include/hw/riscv/sifive_u.h | 16 ++++++- > 2 files changed, 82 insertions(+), 24 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9f3d184b72..4924f92262 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -114,10 +114,10 @@ static void create_fdt(SiFiveUState *s, const struct > MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > > - for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { > + for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { > nodename = g_strdup_printf("/cpus/cpu@%d", cpu); > char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", > cpu); > - char *isa = riscv_isa_string(&s->soc.harts[cpu]); > + char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); > qemu_fdt_add_subnode(fdt, nodename); > qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > SIFIVE_U_CLOCK_FREQ); > @@ -138,8 +138,8 @@ static void create_fdt(SiFiveUState *s, const struct > MemmapEntry *memmap, > g_free(nodename); > } > > - cells = g_new0(uint32_t, s->soc.num_harts * 4); > - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { > + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); > + for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { > nodename = > g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); > uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); > @@ -157,12 +157,12 @@ static void create_fdt(SiFiveUState *s, const struct > MemmapEntry *memmap, > 0x0, memmap[SIFIVE_U_CLINT].base, > 0x0, memmap[SIFIVE_U_CLINT].size); > qemu_fdt_setprop(fdt, nodename, "interrupts-extended", > - cells, s->soc.num_harts * sizeof(uint32_t) * 4); > + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); > g_free(cells); > g_free(nodename); > > - cells = g_new0(uint32_t, s->soc.num_harts * 4); > - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { > + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); > + for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { > nodename = > g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); > uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); > @@ -179,7 +179,7 @@ static void create_fdt(SiFiveUState *s, const struct > MemmapEntry *memmap, > qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); > qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); > qemu_fdt_setprop(fdt, nodename, "interrupts-extended", > - cells, s->soc.num_harts * sizeof(uint32_t) * 4); > + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); > qemu_fdt_setprop_cells(fdt, nodename, "reg", > 0x0, memmap[SIFIVE_U_PLIC].base, > 0x0, memmap[SIFIVE_U_PLIC].size); > @@ -215,17 +215,12 @@ static void riscv_sifive_u_init(MachineState > *machine) > SiFiveUState *s = g_new0(SiFiveUState, 1); > MemoryRegion *system_memory = get_system_memory(); > MemoryRegion *main_mem = g_new(MemoryRegion, 1); > - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); > int i; > > - /* Initialize SOC */ > - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); > + /* Initialize SoC */ > + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U54_SOC); > object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), > &error_abort); > - object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type", > - &error_abort); > - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", > - &error_abort); > object_property_set_bool(OBJECT(&s->soc), true, "realized", > &error_abort); > > @@ -233,17 +228,11 @@ static void riscv_sifive_u_init(MachineState > *machine) > memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", > machine->ram_size, &error_fatal); > memory_region_add_subregion(system_memory, > memmap[SIFIVE_U_DRAM].base, > - main_mem); > + main_mem); > > /* create device tree */ > create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); > > - /* boot rom */ > - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", > - memmap[SIFIVE_U_MROM].size, &error_fatal); > - memory_region_add_subregion(system_memory, > memmap[SIFIVE_U_MROM].base, > - mask_rom); > - > if (machine->kernel_filename) { > load_kernel(machine->kernel_filename); > } > @@ -282,6 +271,39 @@ static void riscv_sifive_u_init(MachineState > *machine) > rom_add_blob_fixed_as("mrom.fdt", s->fdt, s->fdt_size, > memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), > &address_space_memory); > +} > + > +static void riscv_sifive_u54_init(Object *obj) > +{ > + const struct MemmapEntry *memmap = sifive_u_memmap; > + > + SiFiveU54State *s = RISCV_U54_SOC(obj); > + MemoryRegion *system_memory = get_system_memory(); > + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); > + > + object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); > + object_property_add_child(obj, "cpus", OBJECT(&s->cpus), > + &error_abort); > + object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", > + &error_abort); > + object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", > + &error_abort); > + > + /* boot rom */ > + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", > + memmap[SIFIVE_U_MROM].size, &error_fatal); > + memory_region_add_subregion(system_memory, > memmap[SIFIVE_U_MROM].base, > + mask_rom); > +} > + > +static void riscv_sifive_u54_realize(DeviceState *dev, Error **errp) > +{ > + SiFiveU54State *s = RISCV_U54_SOC(dev); > + const struct MemmapEntry *memmap = sifive_u_memmap; > + MemoryRegion *system_memory = get_system_memory(); > + > + object_property_set_bool(OBJECT(&s->cpus), true, "realized", > + &error_abort); > > /* MMIO */ > s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, > @@ -312,3 +334,27 @@ static void riscv_sifive_u_machine_init(MachineClass > *mc) > } > > DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) > + > +static void riscv_sifive_u54_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(oc); > + > + dc->realize = riscv_sifive_u54_realize; > + /* Reason: Uses serial_hds in realize function, thus can't be used > twice */ > + dc->user_creatable = false; > +} > + > +static const TypeInfo riscv_sifive_u54_type_info = { > + .name = TYPE_RISCV_U54_SOC, > + .parent = TYPE_DEVICE, > + .instance_size = sizeof(SiFiveU54State), > + .instance_init = riscv_sifive_u54_init, > + .class_init = riscv_sifive_u54_class_init, > +}; > + > +static void riscv_sifive_u54_register_types(void) > +{ > + type_register_static(&riscv_sifive_u54_type_info); > +} > + > +type_init(riscv_sifive_u54_register_types) > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 94a390566e..0f8bdd8fab 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -19,13 +19,25 @@ > #ifndef HW_SIFIVE_U_H > #define HW_SIFIVE_U_H > > -typedef struct SiFiveUState { > +#define TYPE_RISCV_U54_SOC "riscv.sifive.u54" > +#define RISCV_U54_SOC(obj) \ > + OBJECT_CHECK(SiFiveU54State, (obj), TYPE_RISCV_U54_SOC) > + > +typedef struct SiFiveU54State { > /*< private >*/ > SysBusDevice parent_obj; > > /*< public >*/ > - RISCVHartArrayState soc; > + RISCVHartArrayState cpus; > DeviceState *plic; > +} SiFiveU54State; > + > +typedef struct SiFiveUState { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + SiFiveU54State soc; > void *fdt; > int fdt_size; > } SiFiveUState; > -- > 2.17.0 > >
On Fri, May 4, 2018 at 3:55 PM, Michael Clark <mjc@sifive.com> wrote: > > > On Sat, May 5, 2018 at 8:12 AM, Alistair Francis <alistair.francis@wdc.com> > wrote: >> >> Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. >> >> We leave the SoC, RAM, device tree and reset/fdt loading as part of the >> machine. All the other device creation has been moved to the SoC. > > > There is a tiny problem that we will have to resolve with renaming, > otherwise we will end up with lots of SOCs that are the essentially same > with a different CPU. > > There is an intention to add a HiFive1 and HiFiveU board in the future > however we were very explicit in renaming sifive_e300 and sifive_u500 to > sifive_e and sifive_u. > > If you read the code more closely you'll notice that we instantiate the > sifive_u board with a U34 if 32-bit and a U54 if 64-bit. > > #if defined(TARGET_RISCV32) > #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 > #elif defined(TARGET_RISCV64) > #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 > #endif > > The rationale is that sifive_e and sifive_u can eventually be customized to > represent different configurations of SiFive Core IP. We won't want to end > up hardcoding specific models in sifive_e or sifive_u > > SiFive have been talking internally about having sifive_e and sifive_u > reconfigurable, possibly even to the extend where we can configure with a > memory map. This is somewhat consistent with what SiFive do internally as > the FE310 and FU540 are configurations generated by a core generator. > > Now comes the question of whether its the right time to add a 'hifive1' or > 'hifiveu' machine. I don't think it is immediately necessary. The thought > being that we would be able to give a configuration string of file to > sifive_u e.g. "e51,u54,u54,u54". There is a different between the U54 and > the U54-MC which has an E51 core for management tasks. The PLIC has already > been written with this in mind, and is re-configurable to support the U54-MC > memory layout. Aren't the E51, U54, U54-MC, etc. all different SoCs? So doesn't it make sense to break out the SoCs and then in future the user can specify the SoC for the machine/board when they start QEMU? Alistair > > In anycase. The change is simply to use sifive_u_soc or sifive_u without the > 54 (given it configures with a U34 in 32-bit like the sifive_e configures > with an E51 in 64-bit mode, both valid configurations) >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f3d184b72..4924f92262 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -114,10 +114,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { + for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { nodename = g_strdup_printf("/cpus/cpu@%d", cpu); char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - char *isa = riscv_isa_string(&s->soc.harts[cpu]); + char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); @@ -138,8 +138,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); } - cells = g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); @@ -157,12 +157,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_CLINT].base, 0x0, memmap[SIFIVE_U_CLINT].size); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); g_free(cells); g_free(nodename); - cells = g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu = 0; cpu < s->soc.num_harts; cpu++) { + cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); @@ -179,7 +179,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); @@ -215,17 +215,12 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s = g_new0(SiFiveUState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); int i; - /* Initialize SOC */ - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + /* Initialize SoC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U54_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); - object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); @@ -233,17 +228,11 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, - main_mem); + main_mem); /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, - mask_rom); - if (machine->kernel_filename) { load_kernel(machine->kernel_filename); } @@ -282,6 +271,39 @@ static void riscv_sifive_u_init(MachineState *machine) rom_add_blob_fixed_as("mrom.fdt", s->fdt, s->fdt_size, memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), &address_space_memory); +} + +static void riscv_sifive_u54_init(Object *obj) +{ + const struct MemmapEntry *memmap = sifive_u_memmap; + + SiFiveU54State *s = RISCV_U54_SOC(obj); + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + + object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); + object_property_add_child(obj, "cpus", OBJECT(&s->cpus), + &error_abort); + object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", + &error_abort); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); +} + +static void riscv_sifive_u54_realize(DeviceState *dev, Error **errp) +{ + SiFiveU54State *s = RISCV_U54_SOC(dev); + const struct MemmapEntry *memmap = sifive_u_memmap; + MemoryRegion *system_memory = get_system_memory(); + + object_property_set_bool(OBJECT(&s->cpus), true, "realized", + &error_abort); /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, @@ -312,3 +334,27 @@ static void riscv_sifive_u_machine_init(MachineClass *mc) } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) + +static void riscv_sifive_u54_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = riscv_sifive_u54_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twice */ + dc->user_creatable = false; +} + +static const TypeInfo riscv_sifive_u54_type_info = { + .name = TYPE_RISCV_U54_SOC, + .parent = TYPE_DEVICE, + .instance_size = sizeof(SiFiveU54State), + .instance_init = riscv_sifive_u54_init, + .class_init = riscv_sifive_u54_class_init, +}; + +static void riscv_sifive_u54_register_types(void) +{ + type_register_static(&riscv_sifive_u54_type_info); +} + +type_init(riscv_sifive_u54_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 94a390566e..0f8bdd8fab 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,13 +19,25 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H -typedef struct SiFiveUState { +#define TYPE_RISCV_U54_SOC "riscv.sifive.u54" +#define RISCV_U54_SOC(obj) \ + OBJECT_CHECK(SiFiveU54State, (obj), TYPE_RISCV_U54_SOC) + +typedef struct SiFiveU54State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *plic; +} SiFiveU54State; + +typedef struct SiFiveUState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + SiFiveU54State soc; void *fdt; int fdt_size; } SiFiveUState;
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_u.c | 90 ++++++++++++++++++++++++++++--------- include/hw/riscv/sifive_u.h | 16 ++++++- 2 files changed, 82 insertions(+), 24 deletions(-)