From patchwork Mon Jan 18 15:53:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8055671 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D010FBEEE5 for ; Mon, 18 Jan 2016 15:53:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D196E2045A for ; Mon, 18 Jan 2016 15:53:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D2F220390 for ; Mon, 18 Jan 2016 15:53:53 +0000 (UTC) Received: from localhost ([::1]:60409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLC7s-0004Uw-Et for patchwork-qemu-devel@patchwork.kernel.org; Mon, 18 Jan 2016 10:53:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLC7l-0004Uq-5o for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:53:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLC7k-0002MB-81 for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:53:45 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:59469) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLC7k-0002KW-0s for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:53:44 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1aLC7a-00027Y-A0; Mon, 18 Jan 2016 15:53:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 18 Jan 2016 15:53:34 +0000 Message-Id: <1453132414-8127-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2001:8b0:1d0::1 Cc: "Edgar E. Iglesias" , qemu-arm@linaro.org, patches@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: Implement FPEXC32_EL2 system register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Reviewed-by: Sergey Fedorov --- ARM Trusted Firmware expects this to exist (as does your average hypervisor, I expect). target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 196c111..e8ede3f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2890,6 +2890,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush(CPU(cpu), 1); } +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { + return CP_ACCESS_TRAP_EL2; + } + if (env->cp15.cptr_el[3] & CPTR_TFP) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v8_cp_reginfo[] = { /* Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. @@ -3150,6 +3161,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_RAW, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), + .access = PL2_RW, .accessfn = fpexc32_access }, REGINFO_SENTINEL };