From patchwork Thu Jan 21 14:56:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8082131 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3EC68BEEE5 for ; Thu, 21 Jan 2016 15:04:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C893B2051C for ; Thu, 21 Jan 2016 15:04:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8DF002050E for ; Thu, 21 Jan 2016 15:04:03 +0000 (UTC) Received: from localhost ([::1]:48106 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aMGmI-0008Oa-Vb for patchwork-qemu-devel@patchwork.kernel.org; Thu, 21 Jan 2016 10:04:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aMGfG-0002ZN-OQ for qemu-devel@nongnu.org; Thu, 21 Jan 2016 09:56:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aMGfF-0002nJ-NM for qemu-devel@nongnu.org; Thu, 21 Jan 2016 09:56:46 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:59496) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aMGfF-0002g6-Gu for qemu-devel@nongnu.org; Thu, 21 Jan 2016 09:56:45 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1aMGez-0003QP-Hh for qemu-devel@nongnu.org; Thu, 21 Jan 2016 14:56:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 21 Jan 2016 14:56:05 +0000 Message-Id: <1453388189-13092-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1453388189-13092-1-git-send-email-peter.maydell@linaro.org> References: <1453388189-13092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new method to CPUClass which the memory system core can use to obtain the correct address space index to use for a memory access with a given set of transaction attributes, together with the wrapper function cpu_asidx_from_attrs() which implements the default behaviour ("always use asidx 0") for CPU classes which don't provide the method. Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- include/qom/cpu.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 58605a5..ed23246 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -102,6 +102,8 @@ struct TranslationBlock; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for + * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @debug_excp_handler: Callback for handling debug exceptions. @@ -158,6 +160,7 @@ typedef struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); void (*debug_excp_handler)(CPUState *cpu); @@ -492,6 +495,23 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); } + +/** cpu_asidx_from_attrs: + * @cpu: CPU + * @attrs: memory transaction attributes + * + * Returns the address space index specifying the CPU AddressSpace + * to use for a memory access with the given transaction attributes. + */ +static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (cc->asidx_from_attrs) { + return cc->asidx_from_attrs(cpu, attrs); + } + return 0; +} #endif /**