From patchwork Tue Jan 26 21:32:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 8127761 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E2EFBEEED for ; Tue, 26 Jan 2016 21:38:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 92F3920266 for ; Tue, 26 Jan 2016 21:38:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BBB272022D for ; Tue, 26 Jan 2016 21:38:20 +0000 (UTC) Received: from localhost ([::1]:46982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBJc-0005iZ-67 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 26 Jan 2016 16:38:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBE8-0003s0-7S for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOBE3-0006e3-9A for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:40 -0500 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:8359) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBE3-0006dp-0r for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:35 -0500 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp2-g21.free.fr (Postfix) with ESMTP id D7BBC4B0173; Tue, 26 Jan 2016 22:30:39 +0100 (CET) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Tue, 26 Jan 2016 22:32:08 +0100 Message-Id: <1453843944-26833-4-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453843944-26833-1-git-send-email-hpoussin@reactos.org> References: <1453843944-26833-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 2a01:e0c:1:1599::11 Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , John Snow , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 03/19] i8257: rename struct dma_cont to I8257State X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Hervé Poussineau --- hw/dma/i8257.c | 43 +++++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 4d0b49d..f4fcf39 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -52,7 +52,7 @@ struct dma_regs { #define ADDR 0 #define COUNT 1 -static struct dma_cont { +typedef struct I8257State { uint8_t status; uint8_t command; uint8_t mask; @@ -61,7 +61,9 @@ static struct dma_cont { struct dma_regs regs[4]; MemoryRegion channel_io; MemoryRegion cont_io; -} dma_controllers[2]; +} I8257State; + +static I8257State dma_controllers[2]; enum { CMD_MEMORY_TO_MEMORY = 0x01, @@ -84,7 +86,7 @@ static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; static void write_page (void *opaque, uint32_t nport, uint32_t data) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int ichan; ichan = channels[nport & 7]; @@ -97,7 +99,7 @@ static void write_page (void *opaque, uint32_t nport, uint32_t data) static void write_pageh (void *opaque, uint32_t nport, uint32_t data) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int ichan; ichan = channels[nport & 7]; @@ -110,7 +112,7 @@ static void write_pageh (void *opaque, uint32_t nport, uint32_t data) static uint32_t read_page (void *opaque, uint32_t nport) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int ichan; ichan = channels[nport & 7]; @@ -123,7 +125,7 @@ static uint32_t read_page (void *opaque, uint32_t nport) static uint32_t read_pageh (void *opaque, uint32_t nport) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int ichan; ichan = channels[nport & 7]; @@ -134,7 +136,7 @@ static uint32_t read_pageh (void *opaque, uint32_t nport) return d->regs[ichan].pageh; } -static inline void init_chan (struct dma_cont *d, int ichan) +static inline void init_chan(I8257State *d, int ichan) { struct dma_regs *r; @@ -143,7 +145,7 @@ static inline void init_chan (struct dma_cont *d, int ichan) r->now[COUNT] = 0; } -static inline int getff (struct dma_cont *d) +static inline int getff(I8257State *d) { int ff; @@ -154,7 +156,7 @@ static inline int getff (struct dma_cont *d) static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int ichan, nreg, iport, ff, val, dir; struct dma_regs *r; @@ -177,7 +179,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) static void write_chan(void *opaque, hwaddr nport, uint64_t data, unsigned size) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int iport, ichan, nreg; struct dma_regs *r; @@ -196,7 +198,7 @@ static void write_chan(void *opaque, hwaddr nport, uint64_t data, static void write_cont(void *opaque, hwaddr nport, uint64_t data, unsigned size) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int iport, ichan = 0; iport = (nport >> d->dshift) & 0x0f; @@ -284,7 +286,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) { - struct dma_cont *d = opaque; + I8257State *d = opaque; int iport, val; iport = (nport >> d->dshift) & 0x0f; @@ -361,7 +363,7 @@ static bool dma_bh_scheduled; static void DMA_run (void) { - struct dma_cont *d; + I8257State *d; int icont, ichan; int rearm = 0; static int running = 0; @@ -473,7 +475,7 @@ void DMA_schedule(void) static void dma_reset(void *opaque) { - struct dma_cont *d = opaque; + I8257State *d = opaque; write_cont(d, (0x05 << d->dshift), 0, 1); } @@ -519,7 +521,7 @@ static const MemoryRegionOps cont_io_ops = { }; /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ -static void dma_init2(struct dma_cont *d, int base, int dshift, +static void dma_init2(I8257State *d, int base, int dshift, int page_base, int pageh_base) { int i; @@ -579,11 +581,12 @@ static const VMStateDescription vmstate_dma = { .minimum_version_id = 1, .post_load = dma_post_load, .fields = (VMStateField[]) { - VMSTATE_UINT8(command, struct dma_cont), - VMSTATE_UINT8(mask, struct dma_cont), - VMSTATE_UINT8(flip_flop, struct dma_cont), - VMSTATE_INT32(dshift, struct dma_cont), - VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs), + VMSTATE_UINT8(command, I8257State), + VMSTATE_UINT8(mask, I8257State), + VMSTATE_UINT8(flip_flop, I8257State), + VMSTATE_INT32(dshift, I8257State), + VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_dma_regs, + struct dma_regs), VMSTATE_END_OF_LIST() } };