From patchwork Tue Jan 26 21:32:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 8127771 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B7BCBEEE5 for ; Tue, 26 Jan 2016 21:39:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77608201ED for ; Tue, 26 Jan 2016 21:39:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53F53201DD for ; Tue, 26 Jan 2016 21:39:55 +0000 (UTC) Received: from localhost ([::1]:46995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBL8-0001cN-Md for patchwork-qemu-devel@patchwork.kernel.org; Tue, 26 Jan 2016 16:39:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBE8-0003s3-7M for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOBE3-0006eZ-Vz for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:40 -0500 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:8375) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBE3-0006dz-NU for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:32:35 -0500 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp2-g21.free.fr (Postfix) with ESMTP id A9CA24B00B3; Tue, 26 Jan 2016 22:30:40 +0100 (CET) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Tue, 26 Jan 2016 22:32:10 +0100 Message-Id: <1453843944-26833-6-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453843944-26833-1-git-send-email-hpoussin@reactos.org> References: <1453843944-26833-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 2a01:e0c:1:1599::11 Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , John Snow , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 05/19] i8257: rename functions to start with i8257_ prefix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Hervé Poussineau --- hw/dma/i8257.c | 91 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index e0713a5..b525063 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -80,11 +80,11 @@ enum { }; -static void DMA_run (void); +static void i8257_dma_run(void); static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; -static void write_page (void *opaque, uint32_t nport, uint32_t data) +static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data) { I8257State *d = opaque; int ichan; @@ -97,7 +97,7 @@ static void write_page (void *opaque, uint32_t nport, uint32_t data) d->regs[ichan].page = data; } -static void write_pageh (void *opaque, uint32_t nport, uint32_t data) +static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data) { I8257State *d = opaque; int ichan; @@ -110,7 +110,7 @@ static void write_pageh (void *opaque, uint32_t nport, uint32_t data) d->regs[ichan].pageh = data; } -static uint32_t read_page (void *opaque, uint32_t nport) +static uint32_t i8257_read_page(void *opaque, uint32_t nport) { I8257State *d = opaque; int ichan; @@ -123,7 +123,7 @@ static uint32_t read_page (void *opaque, uint32_t nport) return d->regs[ichan].page; } -static uint32_t read_pageh (void *opaque, uint32_t nport) +static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) { I8257State *d = opaque; int ichan; @@ -136,7 +136,7 @@ static uint32_t read_pageh (void *opaque, uint32_t nport) return d->regs[ichan].pageh; } -static inline void init_chan(I8257State *d, int ichan) +static inline void i8257_init_chan(I8257State *d, int ichan) { I8257Regs *r; @@ -145,7 +145,7 @@ static inline void init_chan(I8257State *d, int ichan) r->now[COUNT] = 0; } -static inline int getff(I8257State *d) +static inline int i8257_getff(I8257State *d) { int ff; @@ -154,7 +154,7 @@ static inline int getff(I8257State *d) return ff; } -static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) +static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size) { I8257State *d = opaque; int ichan, nreg, iport, ff, val, dir; @@ -166,7 +166,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) r = d->regs + ichan; dir = ((r->mode >> 5) & 1) ? -1 : 1; - ff = getff (d); + ff = i8257_getff(d); if (nreg) val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; else @@ -176,8 +176,8 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) return (val >> (d->dshift + (ff << 3))) & 0xff; } -static void write_chan(void *opaque, hwaddr nport, uint64_t data, - unsigned size) +static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, + unsigned int size) { I8257State *d = opaque; int iport, ichan, nreg; @@ -187,16 +187,16 @@ static void write_chan(void *opaque, hwaddr nport, uint64_t data, ichan = iport >> 1; nreg = iport & 1; r = d->regs + ichan; - if (getff (d)) { + if (i8257_getff(d)) { r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); - init_chan (d, ichan); + i8257_init_chan(d, ichan); } else { r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); } } -static void write_cont(void *opaque, hwaddr nport, uint64_t data, - unsigned size) +static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, + unsigned int size) { I8257State *d = opaque; int iport, ichan = 0; @@ -220,7 +220,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, d->status &= ~(1 << (ichan + 4)); } d->status &= ~(1 << ichan); - DMA_run(); + i8257_dma_run(); break; case 0x02: /* single mask */ @@ -228,7 +228,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, d->mask |= 1 << (data & 3); else d->mask &= ~(1 << (data & 3)); - DMA_run(); + i8257_dma_run(); break; case 0x03: /* mode */ @@ -263,12 +263,12 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, case 0x06: /* clear mask for all channels */ d->mask = 0; - DMA_run(); + i8257_dma_run(); break; case 0x07: /* write mask for all channels */ d->mask = data; - DMA_run(); + i8257_dma_run(); break; default: @@ -284,7 +284,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data, #endif } -static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) +static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size) { I8257State *d = opaque; int iport, val; @@ -320,7 +320,7 @@ void DMA_hold_DREQ (int nchan) ichan = nchan & 3; linfo ("held cont=%d chan=%d\n", ncont, ichan); dma_controllers[ncont].status |= 1 << (ichan + 4); - DMA_run(); + i8257_dma_run(); } void DMA_release_DREQ (int nchan) @@ -331,10 +331,10 @@ void DMA_release_DREQ (int nchan) ichan = nchan & 3; linfo ("released cont=%d chan=%d\n", ncont, ichan); dma_controllers[ncont].status &= ~(1 << (ichan + 4)); - DMA_run(); + i8257_dma_run(); } -static void channel_run (int ncont, int ichan) +static void i8257_channel_run(int ncont, int ichan) { int n; I8257Regs *r = &dma_controllers[ncont].regs[ichan]; @@ -361,7 +361,7 @@ static void channel_run (int ncont, int ichan) static QEMUBH *dma_bh; static bool dma_bh_scheduled; -static void DMA_run (void) +static void i8257_dma_run(void) { I8257State *d; int icont, ichan; @@ -384,7 +384,7 @@ static void DMA_run (void) mask = 1 << ichan; if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { - channel_run (icont, ichan); + i8257_channel_run(icont, ichan); rearm = 1; } } @@ -398,10 +398,10 @@ out: } } -static void DMA_run_bh(void *unused) +static void i8257_dma_run_bh(void *unused) { dma_bh_scheduled = false; - DMA_run(); + i8257_dma_run(); } void DMA_register_channel (int nchan, @@ -473,13 +473,14 @@ void DMA_schedule(void) } } -static void dma_reset(void *opaque) +static void i8257_reset(void *opaque) { I8257State *d = opaque; - write_cont(d, (0x05 << d->dshift), 0, 1); + i8257_write_cont(d, (0x05 << d->dshift), 0, 1); } -static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) +static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, + int dma_len) { trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); return dma_pos; @@ -487,8 +488,8 @@ static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) static const MemoryRegionOps channel_io_ops = { - .read = read_chan, - .write = write_chan, + .read = i8257_read_chan, + .write = i8257_write_chan, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, @@ -498,21 +499,21 @@ static const MemoryRegionOps channel_io_ops = { /* IOport from page_base */ static const MemoryRegionPortio page_portio_list[] = { - { 0x01, 3, 1, .write = write_page, .read = read_page, }, - { 0x07, 1, 1, .write = write_page, .read = read_page, }, + { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, }, + { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, }, PORTIO_END_OF_LIST(), }; /* IOport from pageh_base */ static const MemoryRegionPortio pageh_portio_list[] = { - { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, }, - { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, }, + { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, + { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, }, PORTIO_END_OF_LIST(), }; static const MemoryRegionOps cont_io_ops = { - .read = read_cont, - .write = write_cont, + .read = i8257_read_cont, + .write = i8257_write_cont, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, @@ -545,10 +546,10 @@ static void dma_init2(I8257State *d, int base, int dshift, memory_region_add_subregion(isa_address_space_io(NULL), base + (8 << d->dshift), &d->cont_io); - qemu_register_reset(dma_reset, d); - dma_reset(d); + qemu_register_reset(i8257_reset, d); + i8257_reset(d); for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { - d->regs[i].transfer_handler = dma_phony_handler; + d->regs[i].transfer_handler = i8257_phony_handler; } } @@ -568,9 +569,9 @@ static const VMStateDescription vmstate_i8257_regs = { } }; -static int dma_post_load(void *opaque, int version_id) +static int i8257_post_load(void *opaque, int version_id) { - DMA_run(); + i8257_dma_run(); return 0; } @@ -579,7 +580,7 @@ static const VMStateDescription vmstate_dma = { .name = "dma", .version_id = 1, .minimum_version_id = 1, - .post_load = dma_post_load, + .post_load = i8257_post_load, .fields = (VMStateField[]) { VMSTATE_UINT8(command, I8257State), VMSTATE_UINT8(mask, I8257State), @@ -598,5 +599,5 @@ void DMA_init(ISABus *bus, int high_page_enable) vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); - dma_bh = qemu_bh_new(DMA_run_bh, NULL); + dma_bh = qemu_bh_new(i8257_dma_run_bh, NULL); }