diff mbox

[v2,14/14] hw/timer: QOM'ify tusb6010 and remove all tabs

Message ID 1453863375-7618-5-git-send-email-zxq_yx_007@163.com (mailing list archive)
State New, archived
Headers show

Commit Message

zhao xiao qiang Jan. 27, 2016, 2:56 a.m. UTC 
* assign tusb6010_init to tusb6010_info.instance_init and drop the SysBusDeviceClass::init
* use spaces instead of tabs

Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
---
 hw/timer/tusb6010.c | 323 ++++++++++++++++++++++++++--------------------------
 1 file changed, 161 insertions(+), 162 deletions(-)

Comments

Peter Maydell Feb. 15, 2016, 6:20 p.m. UTC | #1 
On 27 January 2016 at 02:56, xiaoqiang zhao <zxq_yx_007@163.com> wrote:
> * assign tusb6010_init to tusb6010_info.instance_init and drop the SysBusDeviceClass::init
> * use spaces instead of tabs

Please don't do whitespace/indentation changes and real
code changes in the same patch. Indent changes should always
go in their own patch if you really need to make them (though
in this case I would not bother personally).

thanks
-- PMM
diff mbox

Patch

diff --git a/hw/timer/tusb6010.c b/hw/timer/tusb6010.c
index 459c748..019ca4c 100644
--- a/hw/timer/tusb6010.c
+++ b/hw/timer/tusb6010.c
@@ -75,170 +75,170 @@  typedef struct TUSBState {
 #define TUSB_BASE_OFFSET		0x400
 
 /* FIFO registers, 32-bit.  */
-#define TUSB_FIFO_BASE			0x600
+#define TUSB_FIFO_BASE                  0x600
 
 /* Device System & Control registers, 32-bit.  */
-#define TUSB_SYS_REG_BASE		0x800
+#define TUSB_SYS_REG_BASE               0x800
 
-#define TUSB_DEV_CONF			(TUSB_SYS_REG_BASE + 0x000)
-#define	TUSB_DEV_CONF_USB_HOST_MODE	(1 << 16)
-#define	TUSB_DEV_CONF_PROD_TEST_MODE	(1 << 15)
-#define	TUSB_DEV_CONF_SOFT_ID		(1 << 1)
-#define	TUSB_DEV_CONF_ID_SEL		(1 << 0)
+#define TUSB_DEV_CONF                   (TUSB_SYS_REG_BASE + 0x000)
+#define TUSB_DEV_CONF_USB_HOST_MODE     (1 << 16)
+#define TUSB_DEV_CONF_PROD_TEST_MODE    (1 << 15)
+#define TUSB_DEV_CONF_SOFT_ID           (1 << 1)
+#define TUSB_DEV_CONF_ID_SEL            (1 << 0)
 
-#define TUSB_PHY_OTG_CTRL_ENABLE	(TUSB_SYS_REG_BASE + 0x004)
-#define TUSB_PHY_OTG_CTRL		(TUSB_SYS_REG_BASE + 0x008)
-#define	TUSB_PHY_OTG_CTRL_WRPROTECT	(0xa5 << 24)
-#define	TUSB_PHY_OTG_CTRL_O_ID_PULLUP	(1 << 23)
-#define	TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN	(1 << 19)
-#define	TUSB_PHY_OTG_CTRL_O_SESS_END_EN	(1 << 18)
-#define	TUSB_PHY_OTG_CTRL_TESTM2	(1 << 17)
-#define	TUSB_PHY_OTG_CTRL_TESTM1	(1 << 16)
-#define	TUSB_PHY_OTG_CTRL_TESTM0	(1 << 15)
-#define	TUSB_PHY_OTG_CTRL_TX_DATA2	(1 << 14)
-#define	TUSB_PHY_OTG_CTRL_TX_GZ2	(1 << 13)
-#define	TUSB_PHY_OTG_CTRL_TX_ENABLE2	(1 << 12)
-#define	TUSB_PHY_OTG_CTRL_DM_PULLDOWN	(1 << 11)
-#define	TUSB_PHY_OTG_CTRL_DP_PULLDOWN	(1 << 10)
-#define	TUSB_PHY_OTG_CTRL_OSC_EN	(1 << 9)
-#define	TUSB_PHY_OTG_CTRL_PHYREF_CLK(v)	(((v) & 3) << 7)
-#define	TUSB_PHY_OTG_CTRL_PD		(1 << 6)
-#define	TUSB_PHY_OTG_CTRL_PLL_ON	(1 << 5)
-#define	TUSB_PHY_OTG_CTRL_EXT_RPU	(1 << 4)
-#define	TUSB_PHY_OTG_CTRL_PWR_GOOD	(1 << 3)
-#define	TUSB_PHY_OTG_CTRL_RESET		(1 << 2)
-#define	TUSB_PHY_OTG_CTRL_SUSPENDM	(1 << 1)
-#define	TUSB_PHY_OTG_CTRL_CLK_MODE	(1 << 0)
+#define TUSB_PHY_OTG_CTRL_ENABLE        (TUSB_SYS_REG_BASE + 0x004)
+#define TUSB_PHY_OTG_CTRL               (TUSB_SYS_REG_BASE + 0x008)
+#define TUSB_PHY_OTG_CTRL_WRPROTECT     (0xa5 << 24)
+#define TUSB_PHY_OTG_CTRL_O_ID_PULLUP   (1 << 23)
+#define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
+#define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
+#define TUSB_PHY_OTG_CTRL_TESTM2        (1 << 17)
+#define TUSB_PHY_OTG_CTRL_TESTM1        (1 << 16)
+#define TUSB_PHY_OTG_CTRL_TESTM0        (1 << 15)
+#define TUSB_PHY_OTG_CTRL_TX_DATA2      (1 << 14)
+#define TUSB_PHY_OTG_CTRL_TX_GZ2        (1 << 13)
+#define TUSB_PHY_OTG_CTRL_TX_ENABLE2    (1 << 12)
+#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN   (1 << 11)
+#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN   (1 << 10)
+#define TUSB_PHY_OTG_CTRL_OSC_EN        (1 << 9)
+#define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
+#define TUSB_PHY_OTG_CTRL_PD            (1 << 6)
+#define TUSB_PHY_OTG_CTRL_PLL_ON        (1 << 5)
+#define TUSB_PHY_OTG_CTRL_EXT_RPU       (1 << 4)
+#define TUSB_PHY_OTG_CTRL_PWR_GOOD      (1 << 3)
+#define TUSB_PHY_OTG_CTRL_RESET         (1 << 2)
+#define TUSB_PHY_OTG_CTRL_SUSPENDM      (1 << 1)
+#define TUSB_PHY_OTG_CTRL_CLK_MODE      (1 << 0)
 
 /* OTG status register */
-#define TUSB_DEV_OTG_STAT		(TUSB_SYS_REG_BASE + 0x00c)
-#define	TUSB_DEV_OTG_STAT_PWR_CLK_GOOD	(1 << 8)
-#define	TUSB_DEV_OTG_STAT_SESS_END	(1 << 7)
-#define	TUSB_DEV_OTG_STAT_SESS_VALID	(1 << 6)
-#define	TUSB_DEV_OTG_STAT_VBUS_VALID	(1 << 5)
-#define	TUSB_DEV_OTG_STAT_VBUS_SENSE	(1 << 4)
-#define	TUSB_DEV_OTG_STAT_ID_STATUS	(1 << 3)
-#define	TUSB_DEV_OTG_STAT_HOST_DISCON	(1 << 2)
-#define	TUSB_DEV_OTG_STAT_LINE_STATE	(3 << 0)
-#define	TUSB_DEV_OTG_STAT_DP_ENABLE	(1 << 1)
-#define	TUSB_DEV_OTG_STAT_DM_ENABLE	(1 << 0)
+#define TUSB_DEV_OTG_STAT               (TUSB_SYS_REG_BASE + 0x00c)
+#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD  (1 << 8)
+#define TUSB_DEV_OTG_STAT_SESS_END      (1 << 7)
+#define TUSB_DEV_OTG_STAT_SESS_VALID    (1 << 6)
+#define TUSB_DEV_OTG_STAT_VBUS_VALID    (1 << 5)
+#define TUSB_DEV_OTG_STAT_VBUS_SENSE    (1 << 4)
+#define TUSB_DEV_OTG_STAT_ID_STATUS     (1 << 3)
+#define TUSB_DEV_OTG_STAT_HOST_DISCON   (1 << 2)
+#define TUSB_DEV_OTG_STAT_LINE_STATE    (3 << 0)
+#define TUSB_DEV_OTG_STAT_DP_ENABLE     (1 << 1)
+#define TUSB_DEV_OTG_STAT_DM_ENABLE     (1 << 0)
 
-#define TUSB_DEV_OTG_TIMER		(TUSB_SYS_REG_BASE + 0x010)
-#define TUSB_DEV_OTG_TIMER_ENABLE	(1 << 31)
-#define TUSB_DEV_OTG_TIMER_VAL(v)	((v) & 0x07ffffff)
-#define TUSB_PRCM_REV			(TUSB_SYS_REG_BASE + 0x014)
+#define TUSB_DEV_OTG_TIMER              (TUSB_SYS_REG_BASE + 0x010)
+#define TUSB_DEV_OTG_TIMER_ENABLE       (1 << 31)
+#define TUSB_DEV_OTG_TIMER_VAL(v)       ((v) & 0x07ffffff)
+#define TUSB_PRCM_REV                   (TUSB_SYS_REG_BASE + 0x014)
 
 /* PRCM configuration register */
-#define TUSB_PRCM_CONF			(TUSB_SYS_REG_BASE + 0x018)
-#define	TUSB_PRCM_CONF_SFW_CPEN		(1 << 24)
-#define	TUSB_PRCM_CONF_SYS_CLKSEL(v)	(((v) & 3) << 16)
+#define TUSB_PRCM_CONF                  (TUSB_SYS_REG_BASE + 0x018)
+#define TUSB_PRCM_CONF_SFW_CPEN         (1 << 24)
+#define TUSB_PRCM_CONF_SYS_CLKSEL(v)    (((v) & 3) << 16)
 
 /* PRCM management register */
-#define TUSB_PRCM_MNGMT			(TUSB_SYS_REG_BASE + 0x01c)
-#define	TUSB_PRCM_MNGMT_SRP_FIX_TMR(v)	(((v) & 0xf) << 25)
-#define	TUSB_PRCM_MNGMT_SRP_FIX_EN	(1 << 24)
-#define	TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v)	(((v) & 0xf) << 20)
-#define	TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN	(1 << 19)
-#define	TUSB_PRCM_MNGMT_DFT_CLK_DIS	(1 << 18)
-#define	TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS	(1 << 17)
-#define	TUSB_PRCM_MNGMT_OTG_SESS_END_EN	(1 << 10)
-#define	TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN	(1 << 9)
-#define	TUSB_PRCM_MNGMT_OTG_ID_PULLUP	(1 << 8)
-#define	TUSB_PRCM_MNGMT_15_SW_EN	(1 << 4)
-#define	TUSB_PRCM_MNGMT_33_SW_EN	(1 << 3)
-#define	TUSB_PRCM_MNGMT_5V_CPEN		(1 << 2)
-#define	TUSB_PRCM_MNGMT_PM_IDLE		(1 << 1)
-#define	TUSB_PRCM_MNGMT_DEV_IDLE	(1 << 0)
+#define TUSB_PRCM_MNGMT                 (TUSB_SYS_REG_BASE + 0x01c)
+#define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v)  (((v) & 0xf) << 25)
+#define TUSB_PRCM_MNGMT_SRP_FIX_EN      (1 << 24)
+#define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
+#define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
+#define TUSB_PRCM_MNGMT_DFT_CLK_DIS     (1 << 18)
+#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS   (1 << 17)
+#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
+#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
+#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP   (1 << 8)
+#define TUSB_PRCM_MNGMT_15_SW_EN        (1 << 4)
+#define TUSB_PRCM_MNGMT_33_SW_EN        (1 << 3)
+#define TUSB_PRCM_MNGMT_5V_CPEN         (1 << 2)
+#define TUSB_PRCM_MNGMT_PM_IDLE         (1 << 1)
+#define TUSB_PRCM_MNGMT_DEV_IDLE        (1 << 0)
 
 /* Wake-up source clear and mask registers */
-#define TUSB_PRCM_WAKEUP_SOURCE		(TUSB_SYS_REG_BASE + 0x020)
-#define TUSB_PRCM_WAKEUP_CLEAR		(TUSB_SYS_REG_BASE + 0x028)
-#define TUSB_PRCM_WAKEUP_MASK		(TUSB_SYS_REG_BASE + 0x02c)
-#define	TUSB_PRCM_WAKEUP_RESERVED_BITS	(0xffffe << 13)
-#define	TUSB_PRCM_WGPIO_7		(1 << 12)
-#define	TUSB_PRCM_WGPIO_6		(1 << 11)
-#define	TUSB_PRCM_WGPIO_5		(1 << 10)
-#define	TUSB_PRCM_WGPIO_4		(1 << 9)
-#define	TUSB_PRCM_WGPIO_3		(1 << 8)
-#define	TUSB_PRCM_WGPIO_2		(1 << 7)
-#define	TUSB_PRCM_WGPIO_1		(1 << 6)
-#define	TUSB_PRCM_WGPIO_0		(1 << 5)
-#define	TUSB_PRCM_WHOSTDISCON		(1 << 4)	/* Host disconnect */
-#define	TUSB_PRCM_WBUS			(1 << 3)	/* USB bus resume */
-#define	TUSB_PRCM_WNORCS		(1 << 2)	/* NOR chip select */
-#define	TUSB_PRCM_WVBUS			(1 << 1)	/* OTG PHY VBUS */
-#define	TUSB_PRCM_WID			(1 << 0)	/* OTG PHY ID detect */
+#define TUSB_PRCM_WAKEUP_SOURCE         (TUSB_SYS_REG_BASE + 0x020)
+#define TUSB_PRCM_WAKEUP_CLEAR          (TUSB_SYS_REG_BASE + 0x028)
+#define TUSB_PRCM_WAKEUP_MASK           (TUSB_SYS_REG_BASE + 0x02c)
+#define TUSB_PRCM_WAKEUP_RESERVED_BITS  (0xffffe << 13)
+#define TUSB_PRCM_WGPIO_7               (1 << 12)
+#define TUSB_PRCM_WGPIO_6               (1 << 11)
+#define TUSB_PRCM_WGPIO_5               (1 << 10)
+#define TUSB_PRCM_WGPIO_4               (1 << 9)
+#define TUSB_PRCM_WGPIO_3               (1 << 8)
+#define TUSB_PRCM_WGPIO_2               (1 << 7)
+#define TUSB_PRCM_WGPIO_1               (1 << 6)
+#define TUSB_PRCM_WGPIO_0               (1 << 5)
+#define TUSB_PRCM_WHOSTDISCON           (1 << 4)        /* Host disconnect */
+#define TUSB_PRCM_WBUS                  (1 << 3)        /* USB bus resume */
+#define TUSB_PRCM_WNORCS                (1 << 2)        /* NOR chip select */
+#define TUSB_PRCM_WVBUS                 (1 << 1)        /* OTG PHY VBUS */
+#define TUSB_PRCM_WID                   (1 << 0)        /* OTG PHY ID detect */
 
-#define TUSB_PULLUP_1_CTRL		(TUSB_SYS_REG_BASE + 0x030)
-#define TUSB_PULLUP_2_CTRL		(TUSB_SYS_REG_BASE + 0x034)
-#define TUSB_INT_CTRL_REV		(TUSB_SYS_REG_BASE + 0x038)
-#define TUSB_INT_CTRL_CONF		(TUSB_SYS_REG_BASE + 0x03c)
-#define TUSB_USBIP_INT_SRC		(TUSB_SYS_REG_BASE + 0x040)
-#define TUSB_USBIP_INT_SET		(TUSB_SYS_REG_BASE + 0x044)
-#define TUSB_USBIP_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x048)
-#define TUSB_USBIP_INT_MASK		(TUSB_SYS_REG_BASE + 0x04c)
-#define TUSB_DMA_INT_SRC		(TUSB_SYS_REG_BASE + 0x050)
-#define TUSB_DMA_INT_SET		(TUSB_SYS_REG_BASE + 0x054)
-#define TUSB_DMA_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x058)
-#define TUSB_DMA_INT_MASK		(TUSB_SYS_REG_BASE + 0x05c)
-#define TUSB_GPIO_INT_SRC		(TUSB_SYS_REG_BASE + 0x060)
-#define TUSB_GPIO_INT_SET		(TUSB_SYS_REG_BASE + 0x064)
-#define TUSB_GPIO_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x068)
-#define TUSB_GPIO_INT_MASK		(TUSB_SYS_REG_BASE + 0x06c)
+#define TUSB_PULLUP_1_CTRL              (TUSB_SYS_REG_BASE + 0x030)
+#define TUSB_PULLUP_2_CTRL              (TUSB_SYS_REG_BASE + 0x034)
+#define TUSB_INT_CTRL_REV               (TUSB_SYS_REG_BASE + 0x038)
+#define TUSB_INT_CTRL_CONF              (TUSB_SYS_REG_BASE + 0x03c)
+#define TUSB_USBIP_INT_SRC              (TUSB_SYS_REG_BASE + 0x040)
+#define TUSB_USBIP_INT_SET              (TUSB_SYS_REG_BASE + 0x044)
+#define TUSB_USBIP_INT_CLEAR            (TUSB_SYS_REG_BASE + 0x048)
+#define TUSB_USBIP_INT_MASK             (TUSB_SYS_REG_BASE + 0x04c)
+#define TUSB_DMA_INT_SRC                (TUSB_SYS_REG_BASE + 0x050)
+#define TUSB_DMA_INT_SET                (TUSB_SYS_REG_BASE + 0x054)
+#define TUSB_DMA_INT_CLEAR              (TUSB_SYS_REG_BASE + 0x058)
+#define TUSB_DMA_INT_MASK               (TUSB_SYS_REG_BASE + 0x05c)
+#define TUSB_GPIO_INT_SRC               (TUSB_SYS_REG_BASE + 0x060)
+#define TUSB_GPIO_INT_SET               (TUSB_SYS_REG_BASE + 0x064)
+#define TUSB_GPIO_INT_CLEAR             (TUSB_SYS_REG_BASE + 0x068)
+#define TUSB_GPIO_INT_MASK              (TUSB_SYS_REG_BASE + 0x06c)
 
 /* NOR flash interrupt source registers */
-#define TUSB_INT_SRC			(TUSB_SYS_REG_BASE + 0x070)
-#define TUSB_INT_SRC_SET		(TUSB_SYS_REG_BASE + 0x074)
-#define TUSB_INT_SRC_CLEAR		(TUSB_SYS_REG_BASE + 0x078)
-#define TUSB_INT_MASK			(TUSB_SYS_REG_BASE + 0x07c)
-#define	TUSB_INT_SRC_TXRX_DMA_DONE	(1 << 24)
-#define	TUSB_INT_SRC_USB_IP_CORE	(1 << 17)
-#define	TUSB_INT_SRC_OTG_TIMEOUT	(1 << 16)
-#define	TUSB_INT_SRC_VBUS_SENSE_CHNG	(1 << 15)
-#define	TUSB_INT_SRC_ID_STATUS_CHNG	(1 << 14)
-#define	TUSB_INT_SRC_DEV_WAKEUP		(1 << 13)
-#define	TUSB_INT_SRC_DEV_READY		(1 << 12)
-#define	TUSB_INT_SRC_USB_IP_TX		(1 << 9)
-#define	TUSB_INT_SRC_USB_IP_RX		(1 << 8)
-#define	TUSB_INT_SRC_USB_IP_VBUS_ERR	(1 << 7)
-#define	TUSB_INT_SRC_USB_IP_VBUS_REQ	(1 << 6)
-#define	TUSB_INT_SRC_USB_IP_DISCON	(1 << 5)
-#define	TUSB_INT_SRC_USB_IP_CONN	(1 << 4)
-#define	TUSB_INT_SRC_USB_IP_SOF		(1 << 3)
-#define	TUSB_INT_SRC_USB_IP_RST_BABBLE	(1 << 2)
-#define	TUSB_INT_SRC_USB_IP_RESUME	(1 << 1)
-#define	TUSB_INT_SRC_USB_IP_SUSPEND	(1 << 0)
+#define TUSB_INT_SRC                    (TUSB_SYS_REG_BASE + 0x070)
+#define TUSB_INT_SRC_SET                (TUSB_SYS_REG_BASE + 0x074)
+#define TUSB_INT_SRC_CLEAR              (TUSB_SYS_REG_BASE + 0x078)
+#define TUSB_INT_MASK                   (TUSB_SYS_REG_BASE + 0x07c)
+#define TUSB_INT_SRC_TXRX_DMA_DONE      (1 << 24)
+#define TUSB_INT_SRC_USB_IP_CORE        (1 << 17)
+#define TUSB_INT_SRC_OTG_TIMEOUT        (1 << 16)
+#define TUSB_INT_SRC_VBUS_SENSE_CHNG    (1 << 15)
+#define TUSB_INT_SRC_ID_STATUS_CHNG     (1 << 14)
+#define TUSB_INT_SRC_DEV_WAKEUP         (1 << 13)
+#define TUSB_INT_SRC_DEV_READY          (1 << 12)
+#define TUSB_INT_SRC_USB_IP_TX          (1 << 9)
+#define TUSB_INT_SRC_USB_IP_RX          (1 << 8)
+#define TUSB_INT_SRC_USB_IP_VBUS_ERR    (1 << 7)
+#define TUSB_INT_SRC_USB_IP_VBUS_REQ    (1 << 6)
+#define TUSB_INT_SRC_USB_IP_DISCON      (1 << 5)
+#define TUSB_INT_SRC_USB_IP_CONN        (1 << 4)
+#define TUSB_INT_SRC_USB_IP_SOF         (1 << 3)
+#define TUSB_INT_SRC_USB_IP_RST_BABBLE  (1 << 2)
+#define TUSB_INT_SRC_USB_IP_RESUME      (1 << 1)
+#define TUSB_INT_SRC_USB_IP_SUSPEND     (1 << 0)
 
-#define TUSB_GPIO_REV			(TUSB_SYS_REG_BASE + 0x080)
-#define TUSB_GPIO_CONF			(TUSB_SYS_REG_BASE + 0x084)
-#define TUSB_DMA_CTRL_REV		(TUSB_SYS_REG_BASE + 0x100)
-#define TUSB_DMA_REQ_CONF		(TUSB_SYS_REG_BASE + 0x104)
-#define TUSB_EP0_CONF			(TUSB_SYS_REG_BASE + 0x108)
-#define TUSB_EP_IN_SIZE			(TUSB_SYS_REG_BASE + 0x10c)
-#define TUSB_DMA_EP_MAP			(TUSB_SYS_REG_BASE + 0x148)
-#define TUSB_EP_OUT_SIZE		(TUSB_SYS_REG_BASE + 0x14c)
-#define TUSB_EP_MAX_PACKET_SIZE_OFFSET	(TUSB_SYS_REG_BASE + 0x188)
-#define TUSB_SCRATCH_PAD		(TUSB_SYS_REG_BASE + 0x1c4)
-#define TUSB_WAIT_COUNT			(TUSB_SYS_REG_BASE + 0x1c8)
-#define TUSB_PROD_TEST_RESET		(TUSB_SYS_REG_BASE + 0x1d8)
+#define TUSB_GPIO_REV                   (TUSB_SYS_REG_BASE + 0x080)
+#define TUSB_GPIO_CONF                  (TUSB_SYS_REG_BASE + 0x084)
+#define TUSB_DMA_CTRL_REV               (TUSB_SYS_REG_BASE + 0x100)
+#define TUSB_DMA_REQ_CONF               (TUSB_SYS_REG_BASE + 0x104)
+#define TUSB_EP0_CONF                   (TUSB_SYS_REG_BASE + 0x108)
+#define TUSB_EP_IN_SIZE                 (TUSB_SYS_REG_BASE + 0x10c)
+#define TUSB_DMA_EP_MAP                 (TUSB_SYS_REG_BASE + 0x148)
+#define TUSB_EP_OUT_SIZE                (TUSB_SYS_REG_BASE + 0x14c)
+#define TUSB_EP_MAX_PACKET_SIZE_OFFSET  (TUSB_SYS_REG_BASE + 0x188)
+#define TUSB_SCRATCH_PAD                (TUSB_SYS_REG_BASE + 0x1c4)
+#define TUSB_WAIT_COUNT                 (TUSB_SYS_REG_BASE + 0x1c8)
+#define TUSB_PROD_TEST_RESET            (TUSB_SYS_REG_BASE + 0x1d8)
 
-#define TUSB_DIDR1_LO			(TUSB_SYS_REG_BASE + 0x1f8)
-#define TUSB_DIDR1_HI			(TUSB_SYS_REG_BASE + 0x1fc)
+#define TUSB_DIDR1_LO                   (TUSB_SYS_REG_BASE + 0x1f8)
+#define TUSB_DIDR1_HI                   (TUSB_SYS_REG_BASE + 0x1fc)
 
 /* Device System & Control register bitfields */
-#define TUSB_INT_CTRL_CONF_INT_RLCYC(v)	(((v) & 0x7) << 18)
-#define TUSB_INT_CTRL_CONF_INT_POLARITY	(1 << 17)
-#define TUSB_INT_CTRL_CONF_INT_MODE	(1 << 16)
-#define TUSB_GPIO_CONF_DMAREQ(v)	(((v) & 0x3f) << 24)
-#define TUSB_DMA_REQ_CONF_BURST_SIZE(v)	(((v) & 3) << 26)
-#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v)	(((v) & 0x3f) << 20)
-#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v)	(((v) & 0xf) << 16)
-#define TUSB_EP0_CONFIG_SW_EN		(1 << 8)
-#define TUSB_EP0_CONFIG_DIR_TX		(1 << 7)
-#define TUSB_EP0_CONFIG_XFR_SIZE(v)	((v) & 0x7f)
-#define TUSB_EP_CONFIG_SW_EN		(1 << 31)
-#define TUSB_EP_CONFIG_XFR_SIZE(v)	((v) & 0x7fffffff)
-#define TUSB_PROD_TEST_RESET_VAL	0xa596
+#define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
+#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
+#define TUSB_INT_CTRL_CONF_INT_MODE     (1 << 16)
+#define TUSB_GPIO_CONF_DMAREQ(v)        (((v) & 0x3f) << 24)
+#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
+#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v)  (((v) & 0x3f) << 20)
+#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
+#define TUSB_EP0_CONFIG_SW_EN           (1 << 8)
+#define TUSB_EP0_CONFIG_DIR_TX          (1 << 7)
+#define TUSB_EP0_CONFIG_XFR_SIZE(v)     ((v) & 0x7f)
+#define TUSB_EP_CONFIG_SW_EN            (1 << 31)
+#define TUSB_EP_CONFIG_XFR_SIZE(v)      ((v) & 0x7fffffff)
+#define TUSB_PROD_TEST_RESET_VAL        0xa596
 
 static void tusb_intr_update(TUSBState *s)
 {
@@ -335,7 +335,7 @@  static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
 
     case TUSB_PHY_OTG_CTRL_ENABLE:
     case TUSB_PHY_OTG_CTRL:
-        return 0x00;	/* TODO */
+        return 0x00;    /* TODO */
 
     case TUSB_DEV_OTG_STAT:
         ret = s->otg_status;
@@ -354,7 +354,7 @@  static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
     case TUSB_PRCM_MNGMT:
         return s->prcm_mngmt;
     case TUSB_PRCM_WAKEUP_SOURCE:
-    case TUSB_PRCM_WAKEUP_CLEAR:	/* TODO: What does this one return?  */
+    case TUSB_PRCM_WAKEUP_CLEAR:        /* TODO: What does this one return?  */
         return 0x00000000;
     case TUSB_PRCM_WAKEUP_MASK:
         return s->wkup_mask;
@@ -370,20 +370,20 @@  static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
         return s->control_config;
 
     case TUSB_USBIP_INT_SRC:
-    case TUSB_USBIP_INT_SET:	/* TODO: What do these two return?  */
+    case TUSB_USBIP_INT_SET:    /* TODO: What do these two return?  */
     case TUSB_USBIP_INT_CLEAR:
         return s->usbip_intr;
     case TUSB_USBIP_INT_MASK:
         return s->usbip_mask;
 
     case TUSB_DMA_INT_SRC:
-    case TUSB_DMA_INT_SET:	/* TODO: What do these two return?  */
+    case TUSB_DMA_INT_SET:      /* TODO: What do these two return?  */
     case TUSB_DMA_INT_CLEAR:
         return s->dma_intr;
     case TUSB_DMA_INT_MASK:
         return s->dma_mask;
 
-    case TUSB_GPIO_INT_SRC:	/* TODO: What do these two return?  */
+    case TUSB_GPIO_INT_SRC:     /* TODO: What do these two return?  */
     case TUSB_GPIO_INT_SET:
     case TUSB_GPIO_INT_CLEAR:
         return s->gpio_intr;
@@ -391,7 +391,7 @@  static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
         return s->gpio_mask;
 
     case TUSB_INT_SRC:
-    case TUSB_INT_SRC_SET:	/* TODO: What do these two return?  */
+    case TUSB_INT_SRC_SET:      /* TODO: What do these two return?  */
     case TUSB_INT_SRC_CLEAR:
         return s->intr;
     case TUSB_INT_MASK:
@@ -418,9 +418,9 @@  static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
         return s->rx_config[epnum];
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        return 0x00000000;	/* TODO */
+        return 0x00000000;      /* TODO */
     case TUSB_WAIT_COUNT:
-        return 0x00;		/* TODO */
+        return 0x00;            /* TODO */
 
     case TUSB_SCRATCH_PAD:
         return s->scratch;
@@ -509,7 +509,7 @@  static void tusb_async_writew(void *opaque, hwaddr addr,
 
     case TUSB_PHY_OTG_CTRL_ENABLE:
     case TUSB_PHY_OTG_CTRL:
-        return;		/* TODO */
+        return;         /* TODO */
     case TUSB_DEV_OTG_TIMER:
         s->otg_timer_val = value;
         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
@@ -622,9 +622,9 @@  static void tusb_async_writew(void *opaque, hwaddr addr,
         break;
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        return;		/* TODO */
+        return;         /* TODO */
     case TUSB_WAIT_COUNT:
-        return;		/* TODO */
+        return;         /* TODO */
 
     case TUSB_SCRATCH_PAD:
         s->scratch = value;
@@ -747,7 +747,7 @@  static void tusb6010_reset(DeviceState *dev)
     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
     s->host_mode = 0;
     s->dev_config = 0;
-    s->otg_status = 0;	/* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
+    s->otg_status = 0;  /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
     s->power = 0;
     s->mask = 0xffffffff;
     s->intr = 0x00000000;
@@ -775,10 +775,11 @@  static void tusb6010_reset(DeviceState *dev)
     musb_reset(s->musb);
 }
 
-static int tusb6010_init(SysBusDevice *sbd)
+static void tusb6010_init(Object *obj)
 {
-    DeviceState *dev = DEVICE(sbd);
-    TUSBState *s = TUSB(dev);
+    DeviceState *dev = DEVICE(obj);
+    TUSBState *s = TUSB(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
     s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
@@ -789,15 +790,12 @@  static int tusb6010_init(SysBusDevice *sbd)
     sysbus_init_irq(sbd, &s->irq);
     qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
     s->musb = musb_init(dev, 1);
-    return 0;
 }
 
 static void tusb6010_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-    k->init = tusb6010_init;
     dc->reset = tusb6010_reset;
 }
 
@@ -805,6 +803,7 @@  static const TypeInfo tusb6010_info = {
     .name          = TYPE_TUSB6010,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(TUSBState),
+    .instance_init = tusb6010_init,
     .class_init    = tusb6010_class_init,
 };