From patchwork Tue Feb 9 17:13:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 8264071 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1BB349F4DD for ; Tue, 9 Feb 2016 17:13:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4C55120268 for ; Tue, 9 Feb 2016 17:13:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D18720263 for ; Tue, 9 Feb 2016 17:13:43 +0000 (UTC) Received: from localhost ([::1]:58478 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTBrC-0007gS-IK for patchwork-qemu-devel@patchwork.kernel.org; Tue, 09 Feb 2016 12:13:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTBqu-0007a9-1q for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:13:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTBqs-0007JW-Iu for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:13:23 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41897) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTBqs-0007JO-Bx for qemu-devel@nongnu.org; Tue, 09 Feb 2016 12:13:22 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id 1BB342C9DA7; Tue, 9 Feb 2016 17:13:22 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-112-25.ams2.redhat.com [10.36.112.25]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u19HDDHF024623; Tue, 9 Feb 2016 12:13:21 -0500 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 9 Feb 2016 18:13:12 +0100 Message-Id: <1455037993-25461-5-git-send-email-pbonzini@redhat.com> In-Reply-To: <1455037993-25461-1-git-send-email-pbonzini@redhat.com> References: <1455037993-25461-1-git-send-email-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: rth@twiddle.net Subject: [Qemu-devel] [PATCH 4/5] target-i386: Implement XSAVEOPT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson Note the cpu.c change -- don't advertise more XSAVE features than we implement. Signed-off-by: Richard Henderson Message-Id: <1436429849-18052-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini --- target-i386/cpu.c | 2 +- target-i386/fpu_helper.c | 38 ++++++++++++++++++++++++++++---------- target-i386/helper.h | 1 + target-i386/translate.c | 22 ++++++++++++++++++++-- 4 files changed, 50 insertions(+), 13 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ae24b75..b500419 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -440,7 +440,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_eax = 0xd, .cpuid_needs_ecx = true, .cpuid_ecx = 1, .cpuid_reg = R_EAX, - .tcg_features = CPUID_XSAVE_XGETBV1, + .tcg_features = CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1, }, [FEAT_6_EAX] = { .feat_names = cpuid_6_feature_name, diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c index 568a9b8..a8512ea 100644 --- a/target-i386/fpu_helper.c +++ b/target-i386/fpu_helper.c @@ -1196,7 +1196,8 @@ static uint64_t get_xinuse(CPUX86State *env) return -1; } -void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) +static void do_xsave(CPUX86State *env, target_ulong ptr, + uint64_t rfbm, uint64_t inuse, uint64_t opt, uintptr_t retaddr) { uint64_t old_bv, new_bv; @@ -1207,19 +1208,34 @@ void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) /* Never save anything not enabled by XCR0. */ rfbm &= env->xcr0; + opt &= rfbm; - if (rfbm & XSTATE_FP) { - do_xsave_fpu(env, ptr, GETPC()); + if (opt & XSTATE_FP) { + do_xsave_fpu(env, ptr, retaddr); } if (rfbm & XSTATE_SSE) { - do_xsave_mxcsr(env, ptr, GETPC()); - do_xsave_sse(env, ptr, GETPC()); + /* Note that saving MXCSR is not suppressed by XSAVEOPT. */ + do_xsave_mxcsr(env, ptr, retaddr); + } + if (opt & XSTATE_SSE) { + do_xsave_sse(env, ptr, retaddr); } /* Update the XSTATE_BV field. */ - old_bv = cpu_ldq_data_ra(env, ptr + 512, GETPC()); - new_bv = (old_bv & ~rfbm) | (get_xinuse(env) & rfbm); - cpu_stq_data_ra(env, ptr + 512, new_bv, GETPC()); + old_bv = cpu_ldq_data_ra(env, ptr + 512, retaddr); + new_bv = (old_bv & ~rfbm) | (inuse & rfbm); + cpu_stq_data_ra(env, ptr + 512, new_bv, retaddr); +} + +void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm) +{ + do_xsave(env, ptr, rfbm, get_xinuse(env), -1, GETPC()); +} + +void helper_xsaveopt(CPUX86State *env, target_ulong ptr, uint64_t rfbm) +{ + uint64_t inuse = get_xinuse(env); + do_xsave(env, ptr, rfbm, inuse, inuse, GETPC()); } static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t retaddr) @@ -1349,8 +1365,10 @@ uint64_t helper_xgetbv(CPUX86State *env, uint32_t ecx) case 0: return env->xcr0; case 1: - /* FIXME: #GP if !CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2]. */ - return env->xcr0 & get_xinuse(env); + if (env->features[FEAT_XSAVE] & CPUID_XSAVE_XGETBV1) { + return env->xcr0 & get_xinuse(env); + } + break; } raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } diff --git a/target-i386/helper.h b/target-i386/helper.h index 9dfc735..9a83955 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -188,6 +188,7 @@ DEF_HELPER_3(frstor, void, env, tl, int) DEF_HELPER_FLAGS_2(fxsave, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(fxrstor, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(xsave, TCG_CALL_NO_WG, void, env, tl, i64) +DEF_HELPER_FLAGS_3(xsaveopt, TCG_CALL_NO_WG, void, env, tl, i64) DEF_HELPER_FLAGS_3(xrstor, TCG_CALL_NO_WG, void, env, tl, i64) DEF_HELPER_FLAGS_2(xgetbv, TCG_CALL_NO_WG, i64, env, i32) DEF_HELPER_FLAGS_3(xsetbv, TCG_CALL_NO_WG, void, env, i32, i64) diff --git a/target-i386/translate.c b/target-i386/translate.c index 8301270..b84ce3b 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -127,6 +127,7 @@ typedef struct DisasContext { int cpuid_ext2_features; int cpuid_ext3_features; int cpuid_7_0_ebx_features; + int cpuid_xsave_features; } DisasContext; static void gen_eob(DisasContext *s); @@ -7647,10 +7648,26 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_CLWB)) goto illegal_op; gen_nop_modrm(env, s, modrm); - } else { + } else if ((modrm & 0xc7) == 0xc0) { /* mfence */ - if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) + if (!(s->cpuid_features & CPUID_SSE2) + || (s->prefix & PREFIX_LOCK)) { goto illegal_op; + } + /* no-op */ + } else { + /* xsaveopt */ + if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0 + || (s->cpuid_xsave_features & CPUID_XSAVE_XSAVEOPT) == 0 + || (s->flags & HF_OSXSAVE_MASK) == 0 + || (s->prefix & (PREFIX_LOCK | PREFIX_DATA + | PREFIX_REPZ | PREFIX_REPNZ))) { + goto illegal_op; + } + gen_lea_modrm(env, s, modrm); + tcg_gen_concat_tl_i64(cpu_tmp1_i64, cpu_regs[R_EAX], + cpu_regs[R_EDX]); + gen_helper_xsaveopt(cpu_env, cpu_A0, cpu_tmp1_i64); } break; case 7: /* sfence / clflush / clflushopt / pcommit */ @@ -7859,6 +7876,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; + dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; #ifdef TARGET_X86_64 dc->lma = (flags >> HF_LMA_SHIFT) & 1; dc->code64 = (flags >> HF_CS64_SHIFT) & 1;