@@ -3554,7 +3554,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
}
break;
default:
- printf("Branch Error at %x\n", ctx->pc);
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
ctx->bstate = BS_BRANCH;
}
@@ -3629,7 +3629,9 @@ static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
if (tricore_feature(env, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC1_16_SRC_SH:
gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
@@ -3637,6 +3639,8 @@ static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
case OPC1_16_SRC_SHA:
gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3720,6 +3724,8 @@ static void decode_srr_opc(DisasContext *ctx, int op1)
case OPC1_16_SRR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3759,6 +3765,8 @@ static void decode_ssr_opc(DisasContext *ctx, int op1)
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3796,6 +3804,8 @@ static void decode_sc_opc(DisasContext *ctx, int op1)
case OPC1_16_SC_SUB_A:
tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3836,6 +3846,8 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3873,6 +3885,8 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
case OPC1_16_SRO_ST_W:
gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3897,6 +3911,9 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
break;
case OPC2_16_SR_FRET:
gen_fret(ctx);
+ break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -3939,6 +3956,8 @@ static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_16_SR_SAT_HU:
gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4149,6 +4168,8 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
r1 = MASK_OP_SR_S1D(ctx->opcode);
tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4183,6 +4204,8 @@ static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_LD_W:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
@@ -4214,6 +4237,8 @@ static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_LD_HU:
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
@@ -4239,6 +4264,8 @@ static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_SWAP_W:
gen_swap(ctx, r1, temp);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
@@ -4265,6 +4292,8 @@ static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_STUCX:
gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4294,7 +4323,8 @@ static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_ST_W:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
break;
-
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -4319,6 +4349,8 @@ static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_ABS_ST_H:
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -4361,6 +4393,8 @@ static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4393,6 +4427,8 @@ static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4450,6 +4486,8 @@ static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4489,6 +4527,8 @@ static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4525,6 +4565,8 @@ static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_or_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
@@ -4564,6 +4606,8 @@ static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
pos1, pos2, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
@@ -4608,20 +4652,25 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
break;
case OPC2_32_BO_CACHEI_WI_SHORTOFF:
case OPC2_32_BO_CACHEI_W_SHORTOFF:
- /* TODO: Raise illegal opcode trap,
- if !tricore_feature(TRICORE_FEATURE_131) */
+ if (!tricore_feature(env, TRICORE_FEATURE_131)) {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_CACHEI_W_POSTINC:
case OPC2_32_BO_CACHEI_WI_POSTINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_CACHEI_W_PREINC:
case OPC2_32_BO_CACHEI_WI_PREINC:
if (tricore_feature(env, TRICORE_FEATURE_131)) {
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_BO_ST_A_SHORTOFF:
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
@@ -4717,6 +4766,8 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_ST_W_PREINC:
gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -4819,6 +4870,8 @@ static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -4949,6 +5002,8 @@ static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
case OPC2_32_BO_LD_W_PREINC:
gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5059,6 +5114,8 @@ static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -5151,6 +5208,8 @@ static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -5210,6 +5269,8 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
gen_swapmsk(ctx, r1, temp2);
gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
@@ -5247,7 +5308,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_W_LONGOFF:
@@ -5257,44 +5318,46 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_BU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_LD_HU_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_B_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_BOL_ST_H_LONGOFF:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
} else {
- /* raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5360,6 +5423,8 @@ static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RC_XOR:
tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -5558,6 +5623,8 @@ static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
const9, &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -5577,6 +5644,8 @@ static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RC_SYSCALL:
/* TODO: Add exception generation */
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5610,6 +5679,8 @@ static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
const9 = MASK_OP_RC_CONST9(ctx->opcode);
gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5645,6 +5716,8 @@ static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
tcg_temp_free(temp);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5686,6 +5759,8 @@ static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
tcg_temp_free(temp3);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -5732,6 +5807,8 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
tcg_temp_free(temp);
tcg_temp_free(temp2);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5777,6 +5854,8 @@ static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5822,6 +5901,8 @@ static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -5862,7 +5943,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
} else {
- /* TODO: raise illegal opcode trap */
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC1_32_RLC_MOV_U:
@@ -5879,6 +5960,8 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6195,6 +6278,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], &tcg_gen_xor_tl);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6269,6 +6354,8 @@ static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_XOR:
tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -6336,6 +6423,8 @@ static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_SUB_A:
tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6363,6 +6452,8 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
gen_fcall_save_ctx(ctx);
tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_gen_exit_tb(0);
ctx->bstate = BS_BRANCH;
@@ -6504,20 +6595,28 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_CRC32:
if (tricore_feature(env, TRICORE_FEATURE_161)) {
gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_DIV:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_DIV_U:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
cpu_gpr_d[r1], cpu_gpr_d[r2]);
- } /* TODO: else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6622,6 +6721,8 @@ static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(n);
}
@@ -6687,6 +6788,8 @@ static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -6722,6 +6825,8 @@ static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6773,6 +6878,8 @@ static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
width, pos);
}
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6818,6 +6925,8 @@ static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
cpu_gpr_d[r1], cpu_gpr_d[r2]);
tcg_temp_free(temp);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6866,6 +6975,8 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6909,6 +7020,8 @@ static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -6952,6 +7065,8 @@ static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -7065,6 +7180,8 @@ static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -7219,6 +7336,8 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -7345,6 +7464,8 @@ static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -7457,6 +7578,8 @@ static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -7611,6 +7734,8 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -7737,6 +7862,8 @@ static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
cpu_gpr_d[r2], n, MODE_UU);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -7788,6 +7915,8 @@ static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
tmp_pos);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(tmp_pos);
tcg_temp_free(tmp_width);
@@ -7848,6 +7977,8 @@ static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
tcg_temp_free(temp2);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
tcg_temp_free(temp);
}
@@ -7919,7 +8050,9 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
} /* else raise privilege trap */
- } /* else raise illegal opcode trap */
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_SYS_TRAPSV:
/* TODO: raise sticky overflow trap */
@@ -7927,6 +8060,8 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_SYS_TRAPV:
/* TODO: raise overflow trap */
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
@@ -8264,6 +8399,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
break;
+ default:
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
}
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target-tricore/translate.c | 175 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 156 insertions(+), 19 deletions(-)