From patchwork Mon Feb 15 17:22:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8317141 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C2B62C02AE for ; Mon, 15 Feb 2016 17:24:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 31BFF2039C for ; Mon, 15 Feb 2016 17:24:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D6F9203A5 for ; Mon, 15 Feb 2016 17:24:58 +0000 (UTC) Received: from localhost ([::1]:34533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVMtN-0003QL-RP for patchwork-qemu-devel@patchwork.kernel.org; Mon, 15 Feb 2016 12:24:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57114) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVMrb-0000Xa-Li for qemu-devel@nongnu.org; Mon, 15 Feb 2016 12:23:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aVMra-0007oF-RA for qemu-devel@nongnu.org; Mon, 15 Feb 2016 12:23:07 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:57358) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVMra-0007mW-KU; Mon, 15 Feb 2016 12:23:06 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aVMrS-0000y1-CN; Mon, 15 Feb 2016 17:22:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 15 Feb 2016 17:22:57 +0000 Message-Id: <1455556977-3644-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455556977-3644-1-git-send-email-peter.maydell@linaro.org> References: <1455556977-3644-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::1 Cc: "Edgar E. Iglesias" , Sergey Fedorov , qemu-arm@nongnu.org, patches@linaro.org Subject: [Qemu-devel] [PATCH 11/11] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov --- target-arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index e1af9d5..93a0b63 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5182,6 +5182,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) switch (mode) { case ARM_CPU_MODE_USR: + return 0; case ARM_CPU_MODE_SYS: case ARM_CPU_MODE_SVC: case ARM_CPU_MODE_ABT: @@ -5191,6 +5192,15 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) */ + /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + * and CPS are treated as illegal mode changes. + */ + if (write_type == CPSRWriteByInstr && + (env->cp15.hcr_el2 & HCR_TGE) && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && + !arm_is_secure_below_el3(env)) { + return 1; + } return 0; case ARM_CPU_MODE_HYP: return !arm_feature(env, ARM_FEATURE_EL2)