diff mbox

[05/11] target-arm: In cpsr_write() ignore mode switches from User mode

Message ID 1455556977-3644-6-git-send-email-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Peter Maydell Feb. 15, 2016, 5:22 p.m. UTC
The only case where we can attempt a cpsr_write() mode switch from
User is from the gdbstub; all other cases are handled in the
calling code (notably translate.c). Architecturally attempts to
alter the mode bits from user mode are simply ignored (and not
treated as a bad mode switch, which in v8 sets CPSR.IL). Make
mode switches from User ignored in cpsr_write() as well, for
consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Sergey Fedorov Feb. 18, 2016, 5:43 p.m. UTC | #1
On 15.02.2016 20:22, Peter Maydell wrote:
> The only case where we can attempt a cpsr_write() mode switch from
> User is from the gdbstub; all other cases are handled in the
> calling code (notably translate.c). Architecturally attempts to
> alter the mode bits from user mode are simply ignored (and not
> treated as a bad mode switch, which in v8 sets CPSR.IL). Make
> mode switches from User ignored in cpsr_write() as well, for
> consistency.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>

> ---
>  target-arm/helper.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d1919bb..9998a25 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -5282,6 +5282,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
>      env->daif |= val & CPSR_AIF & mask;
>  
>      if (write_type != CPSRWriteRaw &&
> +        (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
>          ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
>          if (bad_mode_switch(env, val & CPSR_M)) {
>              /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index d1919bb..9998a25 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5282,6 +5282,7 @@  void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
     env->daif |= val & CPSR_AIF & mask;
 
     if (write_type != CPSRWriteRaw &&
+        (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
         if (bad_mode_switch(env, val & CPSR_M)) {
             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.