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} - /* Intel IOMMU (VT-d) */ - if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { + + if (g_strcmp0(MACHINE(qdev_get_machine())->iommu, INTEL_IOMMU_STR) == 0) { + /* Intel IOMMU (VT-d) */ mch_init_dmar(mch); + } else if (g_strcmp0(MACHINE(qdev_get_machine())->iommu, AMD_IOMMU_STR) + == 0) { + AMDIOMMUState *iommu_state; + PCIDevice *iommu; + PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); + iommu = pci_create_simple(bus, 0x20, TYPE_AMD_IOMMU_DEVICE); + iommu_state = AMD_IOMMU_DEVICE(iommu); + pci_setup_iommu(bus, bridge_host_amd_iommu, iommu_state); } } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 5dbadb7..0b32bd6 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -27,6 +27,7 @@ #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" #define INTEL_IOMMU_DEVICE(obj) \ OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) +#define INTEL_IOMMU_STR "intel" /* DMAR Hardware Unit Definition address (IOMMU unit) */ #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL