From patchwork Thu Feb 18 14:34:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8350801 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 89BCB9F372 for ; Thu, 18 Feb 2016 14:35:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2ADA20225 for ; Thu, 18 Feb 2016 14:35:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B39E2024D for ; Thu, 18 Feb 2016 14:35:43 +0000 (UTC) Received: from localhost ([::1]:41831 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPgE-0005Fj-An for patchwork-qemu-devel@patchwork.kernel.org; Thu, 18 Feb 2016 09:35:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfq-0005EK-CF for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWPfp-0007ub-FN for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:18 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:38427) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfp-0007rP-86 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:17 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aWPfh-0001pX-8p for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:35:09 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 18 Feb 2016 14:34:43 +0000 Message-Id: <1455806108-6961-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> References: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 11/36] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make get_r13_banked() raise an exception at runtime for the corner case of SRS from System mode, so that we can UNDEF it; this brings us in to line with the ARM ARM's set of permitted CONSTRAINED UNPREDICTABLE choices. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Reviewed-by: Edgar E. Iglesias --- target-arm/op_helper.c | 8 ++++++++ target-arm/translate.c | 9 +++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index cfdbc8d..538887c 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -468,6 +468,14 @@ void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) { + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. + * Other UNPREDICTABLE and UNDEF cases were caught at translate time. + */ + raise_exception(env, EXCP_UDEF, syn_uncategorized(), + exception_target_el(env)); + } + if ((env->uncached_cpsr & CPSR_M) == mode) { return env->regs[13]; } else { diff --git a/target-arm/translate.c b/target-arm/translate.c index 7bceb05..e69145d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s, * -- not a valid mode number * -- a mode that's at a higher exception level * -- Monitor, if we are Non-secure - * For the UNPREDICTABLE cases we choose to UNDEF, except that for - * "current mode is System" we will write a garbage SPSR. - * (This is because we don't have access to our current mode here - * and would have to do a runtime check to UNDEF for System.) + * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns) { gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s, addr = tcg_temp_new_i32(); tmp = tcg_const_i32(mode); + /* get_r13_banked() will raise an exception if called from System mode */ + gen_set_condexec(s); + gen_set_pc_im(s, s->pc - 4); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) { @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); + s->is_jmp = DISAS_UPDATE; } static void disas_arm_insn(DisasContext *s, unsigned int insn)