From patchwork Thu Feb 18 14:34:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8350921 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2BD41C0553 for ; Thu, 18 Feb 2016 14:41:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8757D20306 for ; Thu, 18 Feb 2016 14:41:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B216202A1 for ; Thu, 18 Feb 2016 14:41:38 +0000 (UTC) Received: from localhost ([::1]:41887 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPlx-0008MH-Ft for patchwork-qemu-devel@patchwork.kernel.org; Thu, 18 Feb 2016 09:41:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfx-0005Q8-Fb for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWPfw-0007zz-7f for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:25 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:38427) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfw-0007rP-18 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:24 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aWPfg-0001pD-Vq for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:35:08 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 18 Feb 2016 14:34:38 +0000 Message-Id: <1455806108-6961-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> References: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 06/36] target-arm: Report correct syndrome for FPEXC32_EL2 traps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov --- target-arm/cpu.h | 5 +++++ target-arm/helper.c | 4 ++-- target-arm/op_helper.c | 13 +++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 77f9b51..1623821 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1334,6 +1334,11 @@ typedef enum CPAccessResult { /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, + /* Access fails and results in an exception syndrome for an FP access, + * trapped directly to EL2 or EL3 + */ + CP_ACCESS_TRAP_FP_EL2 = 7, + CP_ACCESS_TRAP_FP_EL3 = 8, } CPAccessResult; /* Access functions for coprocessor registers. These cannot fail and diff --git a/target-arm/helper.c b/target-arm/helper.c index e2b7238..bb913c6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3011,10 +3011,10 @@ static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { - return CP_ACCESS_TRAP_EL2; + return CP_ACCESS_TRAP_FP_EL2; } if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_EL3; + return CP_ACCESS_TRAP_FP_EL3; } return CP_ACCESS_OK; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 4c0980e..049b521 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -500,6 +500,19 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = 3; syndrome = syn_uncategorized(); break; + case CP_ACCESS_TRAP_FP_EL2: + target_el = 2; + /* Since we are an implementation that takes exceptions on a trapped + * conditional insn only if the insn has passed its condition code + * check, we take the IMPDEF choice to always report CV=1 COND=0xe + * (which is also the required value for AArch64 traps). + */ + syndrome = syn_fp_access_trap(1, 0xe, false); + break; + case CP_ACCESS_TRAP_FP_EL3: + target_el = 3; + syndrome = syn_fp_access_trap(1, 0xe, false); + break; default: g_assert_not_reached(); }