diff mbox

target-tricore: fix save_context_upper using env->PSW

Message ID 1455889615-3435-1-git-send-email-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show

Commit Message

Bastian Koppelmann Feb. 19, 2016, 1:46 p.m. UTC 
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Richard Henderson Feb. 23, 2016, 7:54 p.m. UTC | #1 
On 02/19/2016 05:46 AM, Bastian Koppelmann wrote:
> If the cached bits for C, V, SV, AV, or SAV were set, they would
> not be saved during the context save since env->PSW was stored instead
> of properly reading them using psw_read().
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>  target-tricore/op_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 3aa6326..796fe67 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -2279,7 +2279,7 @@  static bool cdc_zero(target_ulong *psw)
 static void save_context_upper(CPUTriCoreState *env, int ea)
 {
     cpu_stl_data(env, ea, env->PCXI);
-    cpu_stl_data(env, ea+4, env->PSW);
+    cpu_stl_data(env, ea+4, psw_read(env));
     cpu_stl_data(env, ea+8, env->gpr_a[10]);
     cpu_stl_data(env, ea+12, env->gpr_a[11]);
     cpu_stl_data(env, ea+16, env->gpr_d[8]);