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[50.194.63.110]) by smtp.gmail.com with ESMTPSA id 200sm12775546qhm.47.2016.02.23.13.12.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Feb 2016 13:12:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Feb 2016 13:11:51 -0800 Message-Id: <1456261920-29900-16-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456261920-29900-1-git-send-email-rth@twiddle.net> References: <1456261920-29900-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c04::234 Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [Qemu-devel] [PATCH v2 15/24] target-sparc: Directly implement easy ldd/std asis X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- target-sparc/translate.c | 111 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 98 insertions(+), 13 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 008b07b..5fd096f 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -1976,6 +1976,7 @@ typedef enum { GET_ASI_HELPER, GET_ASI_EXCP, GET_ASI_DIRECT, + GET_ASI_DTWINX, } ASIType; typedef struct { @@ -2034,18 +2035,26 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) switch (asi) { case ASI_N: /* Nucleus */ case ASI_NL: /* Nucleus LE */ + case ASI_TWINX_N: + case ASI_TWINX_NL: mem_idx = MMU_NUCLEUS_IDX; break; case ASI_AIUP: /* As if user primary */ case ASI_AIUPL: /* As if user primary LE */ + case ASI_TWINX_AIUP: + case ASI_TWINX_AIUP_L: mem_idx = MMU_USER_IDX; break; case ASI_AIUS: /* As if user secondary */ case ASI_AIUSL: /* As if user secondary LE */ + case ASI_TWINX_AIUS: + case ASI_TWINX_AIUS_L: mem_idx = MMU_USER_SECONDARY_IDX; break; case ASI_S: /* Secondary */ case ASI_SL: /* Secondary LE */ + case ASI_TWINX_S: + case ASI_TWINX_SL: if (mem_idx == MMU_USER_IDX) { mem_idx = MMU_USER_SECONDARY_IDX; } else if (mem_idx == MMU_KERNEL_IDX) { @@ -2054,6 +2063,8 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) break; case ASI_P: /* Primary */ case ASI_PL: /* Primary LE */ + case ASI_TWINX_P: + case ASI_TWINX_PL: break; } switch (asi) { @@ -2069,6 +2080,18 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) case ASI_PL: type = GET_ASI_DIRECT; break; + case ASI_TWINX_N: + case ASI_TWINX_NL: + case ASI_TWINX_AIUP: + case ASI_TWINX_AIUP_L: + case ASI_TWINX_AIUS: + case ASI_TWINX_AIUS_L: + case ASI_TWINX_P: + case ASI_TWINX_PL: + case ASI_TWINX_S: + case ASI_TWINX_SL: + type = GET_ASI_DTWINX; + break; } /* The little-endian asis all have bit 3 set. */ if (asi & 8) { @@ -2088,6 +2111,9 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, switch (da.type) { case GET_ASI_EXCP: break; + case GET_ASI_DTWINX: /* Reserved for ldda. */ + gen_exception(dc, TT_ILL_INSN); + break; case GET_ASI_DIRECT: tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop); break; @@ -2124,6 +2150,9 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, switch (da.type) { case GET_ASI_EXCP: break; + case GET_ASI_DTWINX: /* Reserved for stda. */ + gen_exception(dc, TT_ILL_INSN); + break; case GET_ASI_DIRECT: tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); break; @@ -2289,32 +2318,57 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, } } -static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) +static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEQ); + TCGv_i64 hi = gen_dest_gpr(dc, rd); + TCGv_i64 lo = gen_dest_gpr(dc, rd + 1); switch (da.type) { case GET_ASI_EXCP: + return; + + case GET_ASI_DTWINX: + gen_check_align(addr, 15); + tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); break; + + case GET_ASI_DIRECT: + { + TCGv_i64 tmp = tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop); + + /* Note that LE ldda acts as if each 32-bit register + result is byte swapped. Having just performed one + 64-bit bswap, we need now to swap the writebacks. */ + if ((da.memop & MO_BSWAP) == MO_TE) { + tcg_gen_extr32_i64(lo, hi, tmp); + } else { + tcg_gen_extr32_i64(hi, lo, tmp); + } + tcg_temp_free_i64(tmp); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i64 tmp; save_state(dc); gen_helper_ldda_asi(cpu_env, addr, r_asi); tcg_temp_free_i32(r_asi); - tmp = gen_dest_gpr(dc, rd); - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUSPARCState, qt0.high)); - gen_store_gpr(dc, rd, tmp); - tmp = gen_dest_gpr(dc, rd + 1); - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUSPARCState, qt0.low)); - gen_store_gpr(dc, rd + 1, tmp); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUSPARCState, qt0.high)); + tcg_gen_ld_i64(lo, cpu_env, offsetof(CPUSPARCState, qt0.low)); } break; } + + gen_store_gpr(dc, rd, hi); + gen_store_gpr(dc, rd + 1, lo); } static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, @@ -2326,6 +2380,31 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, switch (da.type) { case GET_ASI_EXCP: break; + + case GET_ASI_DTWINX: + gen_check_align(addr, 15); + tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop); + tcg_gen_addi_tl(addr, addr, 8); + tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); + break; + + case GET_ASI_DIRECT: + { + TCGv_i64 t64 = tcg_temp_new_i64(); + + /* Note that LE stda acts as if each 32-bit register result is + byte swapped. We will perform one 64-bit LE store, so now + we must swap the order of the construction. */ + if ((da.memop & MO_BSWAP) == MO_TE) { + tcg_gen_concat32_i64(t64, lo, hi); + } else { + tcg_gen_concat32_i64(t64, hi, lo); + } + tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); + tcg_temp_free_i64(t64); + } + break; + default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -2365,17 +2444,19 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2, } #elif !defined(CONFIG_USER_ONLY) -static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) +static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEQ); TCGv_i64 t64 = tcg_temp_new_i64(); - TCGv lo; + TCGv lo, hi; switch (da.type) { case GET_ASI_EXCP: tcg_temp_free_i64(t64); return; + case GET_ASI_DIRECT: + tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop); + break; default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -2391,6 +2472,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, break; } + hi = gen_dest_gpr(dc, rd); lo = gen_dest_gpr(dc, rd + 1); tcg_gen_extr_i64_i32(lo, hi, t64); tcg_temp_free_i64(t64); @@ -2410,6 +2492,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, switch (da.type) { case GET_ASI_EXCP: break; + case GET_ASI_DIRECT: + tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); + break; default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); @@ -4898,7 +4983,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) if (rd & 1) { goto illegal_insn; } - gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd); + gen_ldda_asi(dc, cpu_addr, insn, rd); goto skip_move; case 0x19: /* ldsba, load signed byte alternate */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);