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[50.194.63.110]) by smtp.gmail.com with ESMTPSA id 200sm12775546qhm.47.2016.02.23.13.12.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Feb 2016 13:12:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Feb 2016 13:12:00 -0800 Message-Id: <1456261920-29900-25-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456261920-29900-1-git-send-email-rth@twiddle.net> References: <1456261920-29900-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c04::232 Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [Qemu-devel] [PATCH v2 24/24] target-sparc: Elide duplicate updates to fprs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- target-sparc/translate.c | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 688594d..e296dca 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -81,6 +81,7 @@ typedef struct DisasContext { int n_t32; int n_ttl; #ifdef TARGET_SPARC64 + int fprs_dirty; int asi; #endif } DisasContext; @@ -138,10 +139,16 @@ static inline TCGv get_temp_tl(DisasContext *dc) return t; } -static inline void gen_update_fprs_dirty(int rd) +static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) - tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2); + int bit = (rd < 32) ? 1 : 2; + /* If we know we've already set this bit within the TB, + we can avoid setting it again. */ + if (!(dc->fprs_dirty & bit)) { + dc->fprs_dirty |= bit; + tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit); + } #endif } @@ -183,7 +190,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, (dst & 1 ? 0 : 32), 32); #endif - gen_update_fprs_dirty(dst); + gen_update_fprs_dirty(dc, dst); } static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) @@ -201,7 +208,7 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) { dst = DFPREG(dst); tcg_gen_mov_i64(cpu_fpr[dst / 2], v); - gen_update_fprs_dirty(dst); + gen_update_fprs_dirty(dc, dst); } static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) @@ -234,14 +241,14 @@ static void gen_op_store_QT0_fpr(unsigned int dst) } #ifdef TARGET_SPARC64 -static void gen_move_Q(unsigned int rd, unsigned int rs) +static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) { rd = QFPREG(rd); rs = QFPREG(rs); tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); - gen_update_fprs_dirty(rd); + gen_update_fprs_dirty(dc, rd); } #endif @@ -1822,7 +1829,7 @@ static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs, gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } #ifdef TARGET_SPARC64 @@ -1834,7 +1841,7 @@ static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, gen(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } #endif @@ -1848,7 +1855,7 @@ static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, @@ -1879,7 +1886,7 @@ static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } #ifdef TARGET_SPARC64 @@ -1966,7 +1973,7 @@ static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, gen(cpu_env, src); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, @@ -1979,7 +1986,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, gen(cpu_env, src); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } /* asi moves */ @@ -2749,7 +2756,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2, cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); - gen_update_fprs_dirty(qd); + gen_update_fprs_dirty(dc, qd); } #ifndef CONFIG_USER_ONLY @@ -3547,7 +3554,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_move_Q(rd, rs2); + gen_move_Q(dc, rd, rs2); break; case 0x6: /* V9 fnegd */ gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); @@ -4097,6 +4104,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x6: /* V9 wrfprs */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); + dc->fprs_dirty = 0; save_state(dc); gen_op_next_insn(); tcg_gen_exit_tb(0); @@ -5198,14 +5206,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto jmp_insn; } gen_ldf_asi(dc, cpu_addr, insn, 4, rd); - gen_update_fprs_dirty(rd); + gen_update_fprs_dirty(dc, rd); goto skip_move; case 0x33: /* V9 lddfa */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_update_fprs_dirty(dc, DFPREG(rd)); goto skip_move; case 0x3d: /* V9 prefetcha, no effect */ goto skip_move; @@ -5215,7 +5223,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto jmp_insn; } gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); goto skip_move; #endif default: @@ -5267,7 +5275,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_helper_ldqf(cpu_env, cpu_addr, r_const); tcg_temp_free_i32(r_const); gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(QFPREG(rd)); + gen_update_fprs_dirty(dc, QFPREG(rd)); } break; case 0x23: /* lddf, load double fpreg */ @@ -5535,6 +5543,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->singlestep = (cs->singlestep_enabled || singlestep); #ifdef TARGET_SPARC64 + dc->fprs_dirty = 0; dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; #endif