From patchwork Thu Feb 25 16:43:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 8425101 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 18EE99F314 for ; Thu, 25 Feb 2016 16:49:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E969202D1 for ; Thu, 25 Feb 2016 16:49:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5C0920212 for ; Thu, 25 Feb 2016 16:49:05 +0000 (UTC) Received: from localhost ([::1]:44464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYz69-0000MU-DJ for patchwork-qemu-devel@patchwork.kernel.org; Thu, 25 Feb 2016 11:49:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38954) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYz4H-00067m-Tg for qemu-devel@nongnu.org; Thu, 25 Feb 2016 11:47:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYz4G-0002wL-St for qemu-devel@nongnu.org; Thu, 25 Feb 2016 11:47:09 -0500 Received: from roura.ac.upc.edu ([147.83.33.10]:38859 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYz49-0002sN-3T; Thu, 25 Feb 2016 11:47:01 -0500 Received: from gw-3.ac.upc.es (gw-3.ac.upc.es [147.83.30.9]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id u1PGhG1D002322; Thu, 25 Feb 2016 17:43:16 +0100 Received: from localhost (unknown [84.88.51.85]) by gw-3.ac.upc.es (Postfix) with ESMTPSA id 353D51F3; Thu, 25 Feb 2016 17:43:16 +0100 (CET) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Thu, 25 Feb 2016 17:43:15 +0100 Message-Id: <145641859552.30295.7821536833590725201.stgit@localhost> X-Mailer: git-send-email 2.7.0 In-Reply-To: <145641857632.30295.407142116443473458.stgit@localhost> References: <145641857632.30295.407142116443473458.stgit@localhost> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id u1PGhG1D002322 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.83.33.10 Cc: Peter Maydell , Guan Xuetao , "open list:ARM" , Eduardo Habkost , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Anthony Green , Mark Cave-Ayland , Jia Liu , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , Leon Alrae , "open list:PowerPC" , Stefan Hajnoczi , Paolo Bonzini , "Edgar E. Iglesias" , Bastian Koppelmann , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v9 3/7] tcg: Add type for vCPU pointers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova Acked-by: Richard Henderson --- target-alpha/translate.c | 2 +- target-arm/translate.c | 2 +- target-arm/translate.h | 2 +- target-cris/translate.c | 2 +- target-i386/translate.c | 2 +- target-lm32/translate.c | 2 +- target-m68k/translate.c | 2 +- target-microblaze/translate.c | 2 +- target-mips/translate.c | 2 +- target-moxie/translate.c | 2 +- target-openrisc/translate.c | 2 +- target-ppc/translate.c | 2 +- target-s390x/translate.c | 2 +- target-sh4/translate.c | 2 +- target-sparc/translate.c | 5 +++-- target-tilegx/translate.c | 2 +- target-tricore/translate.c | 2 +- target-unicore32/translate.c | 2 +- target-xtensa/translate.c | 2 +- tcg/tcg.h | 1 + 20 files changed, 22 insertions(+), 20 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 7b798b0..5b86992 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -93,7 +93,7 @@ typedef enum { } ExitStatus; /* global register indexes */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_std_ir[31]; static TCGv cpu_fir[31]; static TCGv cpu_pc; diff --git a/target-arm/translate.c b/target-arm/translate.c index e69145d..7757dcb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -56,7 +56,7 @@ #define IS_USER(s) (s->user) #endif -TCGv_ptr cpu_env; +TCGv_env cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; diff --git a/target-arm/translate.h b/target-arm/translate.h index 53ef971..82e3f6b 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -70,7 +70,7 @@ typedef struct DisasCompare { } DisasCompare; /* Share the TCG temporaries common between 32 and 64 bit modes. */ -extern TCGv_ptr cpu_env; +extern TCGv_env cpu_env; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; diff --git a/target-cris/translate.c b/target-cris/translate.c index 2a283e0..a73176c 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -60,7 +60,7 @@ #define CC_MASK_NZVC 0xf #define CC_MASK_RNZV 0x10e -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_R[16]; static TCGv cpu_PR[16]; static TCGv cc_x; diff --git a/target-i386/translate.c b/target-i386/translate.c index 9171929..53dee79 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -65,7 +65,7 @@ //#define MACRO_TEST 1 /* global register indexes */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_A0; static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; static TCGv_i32 cpu_cc_op; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 3877993..256a51f 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -44,7 +44,7 @@ #define MEM_INDEX 0 -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; static TCGv cpu_ie; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 085cb6a..7560c3a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -50,7 +50,7 @@ static TCGv_i32 cpu_halted; static TCGv_i32 cpu_exception_index; -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static char cpu_reg_names[3*8*3 + 5*4]; static TCGv cpu_dregs[8]; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 296c4d7..f944965 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -46,7 +46,7 @@ (((src) >> start) & ((1 << (end - start + 1)) - 1)) static TCGv env_debug; -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_SR[18]; static TCGv env_imm; diff --git a/target-mips/translate.c b/target-mips/translate.c index 658926d..3706176 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1353,7 +1353,7 @@ enum { }; /* global register indices */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget, bcond; diff --git a/target-moxie/translate.c b/target-moxie/translate.c index bc860a5..a437e2a 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -56,7 +56,7 @@ enum { static TCGv cpu_pc; static TCGv cpu_gregs[16]; -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cc_a, cc_b; #include "exec/gen-icount.h" diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index d25324e..5d0ab44 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -53,7 +53,7 @@ typedef struct DisasContext { uint32_t delayed_branch; } DisasContext; -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_sr; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ecc85f0..e402ff9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -49,7 +49,7 @@ /* Code translation helpers */ /* global register indexes */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ + 10*4 + 22*5 /* FPR */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 82e1165..c871ef2 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -37,7 +37,7 @@ #include "exec/cpu_ldst.h" /* global register indexes */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; #include "exec/gen-icount.h" #include "exec/helper-proto.h" diff --git a/target-sh4/translate.c b/target-sh4/translate.c index e35d175..7c18968 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -61,7 +61,7 @@ enum { }; /* global register indexes */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_gregs[24]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 00d61ee..58572c3 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -39,7 +39,8 @@ according to jump_pc[T2] */ /* global register indexes */ -static TCGv_ptr cpu_env, cpu_regwptr; +static TCGv_env cpu_env; +static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv_i32 cpu_cc_op; static TCGv_i32 cpu_psr; @@ -2291,7 +2292,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) } #ifndef CONFIG_USER_ONLY -static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) +static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) { TCGv_i32 r_tl = tcg_temp_new_i32(); diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 7073aba..03918eb 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -32,7 +32,7 @@ #define FMT64X "%016" PRIx64 -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_pc; static TCGv cpu_regs[TILEGX_R_COUNT]; diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 6d7f553..d13e5c8 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -47,7 +47,7 @@ static TCGv cpu_PSW_SV; static TCGv cpu_PSW_AV; static TCGv cpu_PSW_SAV; /* CPU env */ -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; #include "exec/gen-icount.h" diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 1dd086d..39af3af 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -48,7 +48,7 @@ typedef struct DisasContext { conditional executions state has been updated. */ #define DISAS_SYSCALL 5 -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; /* FIXME: These should be removed. */ diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fd03603..9894488 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -74,7 +74,7 @@ typedef struct DisasContext { unsigned cpenable; } DisasContext; -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; diff --git a/tcg/tcg.h b/tcg/tcg.h index c45329a..e7983be 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -308,6 +308,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; typedef struct TCGv_ptr_d *TCGv_ptr; +typedef TCGv_ptr TCGv_env; static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i) {