From patchwork Fri Feb 26 15:20:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8438511 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6FCFF9F52D for ; Fri, 26 Feb 2016 15:30:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77BF6203B1 for ; Fri, 26 Feb 2016 15:30:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8A4322024C for ; Fri, 26 Feb 2016 15:30:06 +0000 (UTC) Received: from localhost ([::1]:50517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKLF-0006R3-Qy for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Feb 2016 10:30:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC0-0007Qg-OQ for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZKBz-0004lU-QP for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:32 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:55996) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKBz-0004kv-J7 for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:31 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aZKBx-0003K5-Dx for qemu-devel@nongnu.org; Fri, 26 Feb 2016 15:20:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 26 Feb 2016 15:20:08 +0000 Message-Id: <1456500025-28761-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> References: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/20] target-arm: Raw CPSR writes should skip checks and bank switching X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 5 +++-- target-arm/kvm64.c | 1 - target-arm/machine.c | 2 -- target-arm/op_helper.c | 5 ++++- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 014bb80..c491cd8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5268,7 +5268,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, * In a V8 implementation, it is permitted for privileged software to * change the CPSR A/F bits regardless of the SCR.AW/FW bits. */ - if (!arm_feature(env, ARM_FEATURE_V8) && + if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure(env)) { @@ -5315,7 +5315,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, env->daif &= ~(CPSR_AIF & mask); env->daif |= val & CPSR_AIF & mask; - if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { + if (write_type != CPSRWriteRaw && + ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { if (bad_mode_switch(env, val & CPSR_M)) { /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. * We choose to ignore the attempt and leave the CPSR M field diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 08c2c81..e8527bf 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -722,7 +722,6 @@ int kvm_arch_get_registers(CPUState *cs) if (is_a64(env)) { pstate_write(env, val); } else { - env->uncached_cpsr = val & CPSR_M; cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 0fc7df0..03a73d9 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -173,8 +173,6 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size) return 0; } - /* Avoid mode switch when restoring CPSR */ - env->uncached_cpsr = val & CPSR_M; cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); return 0; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 543d33a..4881e34 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -779,7 +779,10 @@ void HELPER(exception_return)(CPUARMState *env) if (!return_to_aa64) { env->aarch64 = 0; - env->uncached_cpsr = spsr & CPSR_M; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ cpsr_write(env, spsr, ~0, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS;