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[1/3] target-tricore: add missing break in insn decode switch stmt

Message ID 1456852526-3630-2-git-send-email-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show

Commit Message

Bastian Koppelmann March 1, 2016, 5:15 p.m. UTC 
After decoding/translating a RRR_DIVIDE type instruction we would simply
fall through and would decode/translate another unintended RRR2_MADD
instruction.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox

Patch

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 6d7f553..f028fb9 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8632,6 +8632,7 @@  static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
         break;
     case OPCM_32_RRR_DIVIDE:
         decode_rrr_divide(env, ctx);
+        break;
 /* RRR2 Format */
     case OPCM_32_RRR2_MADD:
         decode_rrr2_madd(env, ctx);