From patchwork Fri Mar 4 11:41:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8503241 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 862F7C0553 for ; Fri, 4 Mar 2016 11:48:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD59B201F4 for ; Fri, 4 Mar 2016 11:48:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29842201C7 for ; Fri, 4 Mar 2016 11:48:16 +0000 (UTC) Received: from localhost ([::1]:40552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aboDP-0007WS-JK for patchwork-qemu-devel@patchwork.kernel.org; Fri, 04 Mar 2016 06:48:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abo7R-00053D-LU for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1abo7Q-00019G-Mk for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:05 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:56102) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abo7Q-00018M-GV for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:04 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1abo7Q-0001x3-4N for qemu-devel@nongnu.org; Fri, 04 Mar 2016 11:42:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 4 Mar 2016 11:41:41 +0000 Message-Id: <1457091713-10138-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457091713-10138-1-git-send-email-peter.maydell@linaro.org> References: <1457091713-10138-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Crosthwaite Implement SCTLR.EE bit which controls data endianess for exceptions and page table translations. SCTLR.EE is mirrored to the CPSR.E bit on exception entry. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 0a0e85d..eaded41 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6241,6 +6241,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; + /* Set new mode endianness */ + env->uncached_cpsr &= ~CPSR_E; + if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + env->uncached_cpsr |= ~CPSR_E; + } env->daif |= mask; /* this is a lie, as the was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 */ @@ -6527,6 +6532,12 @@ static inline bool regime_translation_disabled(CPUARMState *env, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +static inline bool regime_translation_big_endian(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; +} + /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -6849,7 +6860,11 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, if (fi->s1ptw) { return 0; } - return address_space_ldl(as, addr, attrs, NULL); + if (regime_translation_big_endian(env, mmu_idx)) { + return address_space_ldl_be(as, addr, attrs, NULL); + } else { + return address_space_ldl_le(as, addr, attrs, NULL); + } } static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, @@ -6867,7 +6882,11 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, if (fi->s1ptw) { return 0; } - return address_space_ldq(as, addr, attrs, NULL); + if (regime_translation_big_endian(env, mmu_idx)) { + return address_space_ldq_be(as, addr, attrs, NULL); + } else { + return address_space_ldq_le(as, addr, attrs, NULL); + } } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,