From patchwork Fri Mar 4 11:41:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8503361 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 314E39F659 for ; Fri, 4 Mar 2016 11:54:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 66F04201F2 for ; Fri, 4 Mar 2016 11:54:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F33A201C7 for ; Fri, 4 Mar 2016 11:54:02 +0000 (UTC) Received: from localhost ([::1]:40615 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aboIz-0001gO-Qd for patchwork-qemu-devel@patchwork.kernel.org; Fri, 04 Mar 2016 06:54:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abo7W-0005EF-Ih for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1abo7S-00019y-2a for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:10 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:56103) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abo7R-00019V-RP for qemu-devel@nongnu.org; Fri, 04 Mar 2016 06:42:06 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1abo7R-0001xr-Dv for qemu-devel@nongnu.org; Fri, 04 Mar 2016 11:42:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 4 Mar 2016 11:41:43 +0000 Message-Id: <1457091713-10138-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457091713-10138-1-git-send-email-peter.maydell@linaro.org> References: <1457091713-10138-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 20/30] target-arm: introduce disas flag for endianness X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paolo Bonzini Introduce a disas flag for setting the CPU data endianness. This allows control of the endianness from the CPU state rather than hard-coding it to TARGET_WORDS_BIGENDIAN. Signed-off-by: Paolo Bonzini [ PC changes: * Split off as new patch from original: "target-arm: introduce tbflag for CPSR.E" * Wrote commit message from scratch ] Reviewed-by: Peter Maydell Signed-off-by: Peter Crosthwaite Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 1 + target-arm/translate.c | 39 ++++++++++++++++++++++++--------------- target-arm/translate.h | 1 + 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f6dd44b..88b95ab 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11032,6 +11032,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; + dc->be_data = MO_TE; dc->condexec_mask = 0; dc->condexec_cond = 0; dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); diff --git a/target-arm/translate.c b/target-arm/translate.c index 41c3c7f..2d4b1cc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -924,26 +924,30 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 addr, int index) \ { \ - tcg_gen_qemu_ld_i32(val, addr, index, (OPC)); \ + TCGMemOp opc = (OPC) | s->be_data; \ + tcg_gen_qemu_ld_i32(val, addr, index, opc); \ } #define DO_GEN_ST(SUFF, OPC) \ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 addr, int index) \ { \ - tcg_gen_qemu_st_i32(val, addr, index, (OPC)); \ + TCGMemOp opc = (OPC) | s->be_data; \ + tcg_gen_qemu_st_i32(val, addr, index, opc); \ } static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, int index) { - tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ); + TCGMemOp opc = MO_Q | s->be_data; + tcg_gen_qemu_ld_i64(val, addr, index, opc); } static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, int index) { - tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ); + TCGMemOp opc = MO_Q | s->be_data; + tcg_gen_qemu_st_i64(val, addr, index, opc); } #else @@ -952,9 +956,10 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 addr, int index) \ { \ + TCGMemOp opc = (OPC) | s->be_data; \ TCGv addr64 = tcg_temp_new(); \ tcg_gen_extu_i32_i64(addr64, addr); \ - tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \ + tcg_gen_qemu_ld_i32(val, addr64, index, opc); \ tcg_temp_free(addr64); \ } @@ -962,27 +967,30 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 addr, int index) \ { \ + TCGMemOp opc = (OPC) | s->be_data; \ TCGv addr64 = tcg_temp_new(); \ tcg_gen_extu_i32_i64(addr64, addr); \ - tcg_gen_qemu_st_i32(val, addr64, index, OPC); \ + tcg_gen_qemu_st_i32(val, addr64, index, opc); \ tcg_temp_free(addr64); \ } static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, int index) { + TCGMemOp opc = MO_Q | s->be_data; TCGv addr64 = tcg_temp_new(); tcg_gen_extu_i32_i64(addr64, addr); - tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ); + tcg_gen_qemu_ld_i64(val, addr64, index, opc); tcg_temp_free(addr64); } static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, int index) { + TCGMemOp opc = MO_Q | s->be_data; TCGv addr64 = tcg_temp_new(); tcg_gen_extu_i32_i64(addr64, addr); - tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ); + tcg_gen_qemu_st_i64(val, addr64, index, opc); tcg_temp_free(addr64); } @@ -990,15 +998,15 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_TESW) -DO_GEN_LD(16u, MO_TEUW) -DO_GEN_LD(32u, MO_TEUL) +DO_GEN_LD(16s, MO_SW) +DO_GEN_LD(16u, MO_UW) +DO_GEN_LD(32u, MO_UL) /* 'a' variants include an alignment check */ -DO_GEN_LD(16ua, MO_TEUW | MO_ALIGN) -DO_GEN_LD(32ua, MO_TEUL | MO_ALIGN) +DO_GEN_LD(16ua, MO_UW | MO_ALIGN) +DO_GEN_LD(32ua, MO_UL | MO_ALIGN) DO_GEN_ST(8, MO_UB) -DO_GEN_ST(16, MO_TEUW) -DO_GEN_ST(32, MO_TEUL) +DO_GEN_ST(16, MO_UW) +DO_GEN_ST(32, MO_UL) static inline void gen_set_pc_im(DisasContext *s, target_ulong val) { @@ -11322,6 +11330,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = ARM_TBFLAG_THUMB(tb->flags); dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags); + dc->be_data = MO_TE; dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags); diff --git a/target-arm/translate.h b/target-arm/translate.h index 5445232..6a18d7b 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -17,6 +17,7 @@ typedef struct DisasContext { int singlestep_enabled; int thumb; int sctlr_b; + TCGMemOp be_data; #if !defined(CONFIG_USER_ONLY) int user; #endif