diff mbox

[v2,1/7] target-tricore: Add FPU infrastructure

Message ID 1457458958-23933-2-git-send-email-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show

Commit Message

Bastian Koppelmann March 8, 2016, 5:42 p.m. UTC
This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v1 -> v2: 
    - add TriCore to softfloat-specialize.h
    - add fpu_set_state() which sets fpu config on psw_write() and cpu_reset
    - add f_get_excp_flags which is used to ignore input_denormal flag
    - note here that f_update_psw_flags() is still inline since it would
      otherwise cause and compiler error. This will be changed in PATCH[03/07].


 fpu/softfloat-specialize.h       |  2 +-
 target-tricore/Makefile.objs     |  2 +-
 target-tricore/cpu.h             |  6 ++-
 target-tricore/fpu_helper.c      | 80 ++++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.c          | 10 +++++
 target-tricore/translate.c       |  1 +
 target-tricore/tricore-opcodes.h | 18 +++++++++
 7 files changed, 115 insertions(+), 4 deletions(-)
 create mode 100644 target-tricore/fpu_helper.c

Comments

Richard Henderson March 8, 2016, 6:26 p.m. UTC | #1
On 03/08/2016 12:42 PM, Bastian Koppelmann wrote:
> +/* we don't care about input_denormal */
> +static inline uint8_t f_get_excp_flags(CPUTriCoreState *env)
> +{
> +    return env->fp_status.float_exception_flags & 0xbf;
> +}

No magic numbers please.  It's a long list, but please or all of the named 
flags together.

> +    if (flags & float_flag_invalid) {
> +        env->FPU_FI = (flags & float_flag_invalid) << 31;
> +    }

You know that float_flag_invalid is set; you just tested it.  Otherwise you're 
relying on float_flag_invalid being 1.

You know, you don't have to keep setting these to (1 << 31) either; -1 works 
just as well.



r~
diff mbox

Patch

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 0875436..a4cbdad 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -113,7 +113,7 @@  const float16 float16_default_nan = const_float16(0xFE00);
 #if defined(TARGET_SPARC)
 const float32 float32_default_nan = const_float32(0x7FFFFFFF);
 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
-      defined(TARGET_XTENSA) || defined(TARGET_S390X)
+      defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE)
 const float32 float32_default_nan = const_float32(0x7FC00000);
 #elif SNAN_BIT_IS_ONE
 const float32 float32_default_nan = const_float32(0x7FBFFFFF);
diff --git a/target-tricore/Makefile.objs b/target-tricore/Makefile.objs
index 21e820d..7a05670 100644
--- a/target-tricore/Makefile.objs
+++ b/target-tricore/Makefile.objs
@@ -1 +1 @@ 
-obj-y += translate.o helper.o cpu.o op_helper.o
+obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index 5fee376..90045a9 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -183,8 +183,7 @@  struct CPUTriCoreState {
     uint32_t M2CNT;
     uint32_t M3CNT;
     /* Floating Point Registers */
-    /* XXX: */
-
+    float_status fp_status;
     /* QEMU */
     int error_code;
     uint32_t hflags;    /* CPU State */
@@ -217,6 +216,7 @@  struct CPUTriCoreState {
 #define MASK_PSW_GW  0x00000100
 #define MASK_PSW_CDE 0x00000080
 #define MASK_PSW_CDC 0x0000007f
+#define MASK_PSW_FPU_RM 0x3000000
 
 #define MASK_SYSCON_PRO_TEN 0x2
 #define MASK_SYSCON_FCD_SF  0x1
@@ -339,6 +339,8 @@  enum {
 uint32_t psw_read(CPUTriCoreState *env);
 void psw_write(CPUTriCoreState *env, uint32_t val);
 
+void fpu_set_state(CPUTriCoreState *env);
+
 #include "cpu-qom.h"
 #define MMU_USER_IDX 2
 
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
new file mode 100644
index 0000000..07a0a1e
--- /dev/null
+++ b/target-tricore/fpu_helper.c
@@ -0,0 +1,80 @@ 
+/*
+ *  TriCore emulation for qemu: fpu helper.
+ *
+ *  Copyright (c) 2016 Bastian Koppelmann University of Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+#define ADD_NAN   0x7cf00001
+#define DIV_NAN   0x7fc00008
+#define MUL_NAN   0x7fc00002
+#define FPU_FS PSW_USB_C
+#define FPU_FI PSW_USB_V
+#define FPU_FV PSW_USB_SV
+#define FPU_FZ PSW_USB_AV
+#define FPU_FU PSW_USB_SAV
+
+/* we don't care about input_denormal */
+static inline uint8_t f_get_excp_flags(CPUTriCoreState *env)
+{
+    return env->fp_status.float_exception_flags & 0xbf;
+}
+
+static inline bool f_is_pos_inf(float32 arg)
+{
+    return !float32_is_neg(arg) && float32_is_infinity(arg);
+}
+
+static inline bool f_is_neg_inf(float32 arg)
+{
+    return float32_is_neg(arg) && float32_is_infinity(arg);
+}
+
+static inline bool f_is_denormal(float32 arg)
+{
+    return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);
+}
+
+static inline void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
+{
+    set_float_exception_flags(0, &env->fp_status);
+
+    if (flags & float_flag_invalid) {
+        env->FPU_FI = (flags & float_flag_invalid) << 31;
+    }
+
+    if (flags & float_flag_overflow) {
+        env->FPU_FV = 1 << 31;
+    }
+
+    if (flags & float_flag_underflow || flags & float_flag_output_denormal) {
+        env->FPU_FU = 1 << 31;
+    }
+
+    if (flags & float_flag_divbyzero) {
+        env->FPU_FZ = 1 << 31;
+    }
+
+    if (flags & float_flag_inexact || flags & float_flag_output_denormal) {
+        env->PSW |= 1 << 26;
+    }
+    /* we assume here that this function is only called if there are exception
+       flags */
+    env->FPU_FS = 1;
+}
diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index 7d96dad..5d0add6 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -110,6 +110,14 @@  void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
     g_slist_free(list);
 }
 
+void fpu_set_state(CPUTriCoreState *env)
+{
+    set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+    set_flush_inputs_to_zero(1, &env->fp_status);
+    set_flush_to_zero(1, &env->fp_status);
+    set_default_nan_mode(1, &env->fp_status);
+}
+
 uint32_t psw_read(CPUTriCoreState *env)
 {
     /* clear all USB bits */
@@ -132,4 +140,6 @@  void psw_write(CPUTriCoreState *env, uint32_t val)
     env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
     env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
     env->PSW = val;
+
+    fpu_set_state(env);
 }
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d13e5c8..06ac41a 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8771,6 +8771,7 @@  void cpu_state_reset(CPUTriCoreState *env)
 {
     /* Reset Regs to Default Value */
     env->PSW = 0xb80;
+    fpu_set_state(env);
 }
 
 static void tricore_tcg_init_csfr(void)
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 1bfed0c..df666b0 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1126,6 +1126,20 @@  enum {
     OPC2_32_RR_CRC32                             = 0x03,
     OPC2_32_RR_DIV                               = 0x20,
     OPC2_32_RR_DIV_U                             = 0x21,
+    OPC2_32_RR_MUL_F                             = 0x04,
+    OPC2_32_RR_DIV_F                             = 0x05,
+    OPC2_32_RR_FTOI                              = 0x10,
+    OPC2_32_RR_ITOF                              = 0x14,
+    OPC2_32_RR_CMP_F                             = 0x00,
+    OPC2_32_RR_FTOIZ                             = 0x13,
+    OPC2_32_RR_FTOQ31                            = 0x11,
+    OPC2_32_RR_FTOQ31Z                           = 0x18,
+    OPC2_32_RR_FTOU                              = 0x12,
+    OPC2_32_RR_FTOUZ                             = 0x17,
+    OPC2_32_RR_Q31TOF                            = 0x15,
+    OPC2_32_RR_QSEED_F                           = 0x19,
+    OPC2_32_RR_UPDFL                             = 0x0c,
+    OPC2_32_RR_UTOF                              = 0x16,
 };
 /* OPCM_32_RR_IDIRECT                               */
 enum {
@@ -1209,6 +1223,10 @@  enum {
     OPC2_32_RRR_IXMIN                            = 0x08,
     OPC2_32_RRR_IXMIN_U                          = 0x09,
     OPC2_32_RRR_PACK                             = 0x00,
+    OPC2_32_RRR_ADD_F                            = 0x02,
+    OPC2_32_RRR_SUB_F                            = 0x03,
+    OPC2_32_RRR_MADD_F                           = 0x06,
+    OPC2_32_RRR_MSUB_F                           = 0x07,
 };
 /*
  * RRR1 Format