From patchwork Tue Mar 15 09:59:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 8586971 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 92A00C0553 for ; Tue, 15 Mar 2016 10:05:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05A4120254 for ; Tue, 15 Mar 2016 10:05:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56E2220121 for ; Tue, 15 Mar 2016 10:05:04 +0000 (UTC) Received: from localhost ([::1]:46949 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflqZ-0001DI-6Z for patchwork-qemu-devel@patchwork.kernel.org; Tue, 15 Mar 2016 06:05:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflmJ-00029I-DW for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aflmF-0007ra-1f for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:39 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:53119) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aflmE-0007rV-TB for qemu-devel@nongnu.org; Tue, 15 Mar 2016 06:00:34 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id D50EB88CFF489; Tue, 15 Mar 2016 10:00:31 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Tue, 15 Mar 2016 10:00:33 +0000 From: Leon Alrae To: Date: Tue, 15 Mar 2016 09:59:36 +0000 Message-ID: <1458035976-23414-12-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1458035976-23414-1-git-send-email-leon.alrae@imgtec.com> References: <1458035976-23414-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, peter.maydell@linaro.org, james.hogan@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 3192db0..b44df9e 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |