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[94.39.161.17]) by smtp.gmail.com with ESMTPSA id wr2sm2418094wjc.49.2016.03.16.03.47.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Mar 2016 03:47:12 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Wed, 16 Mar 2016 11:46:19 +0100 Message-Id: <1458125219-131698-10-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> References: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PATCH 09/49] target-lm32: make cpu-qom.h not target specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make LM32CPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini --- target-lm32/cpu-qom.h | 41 +---------------------------------------- target-lm32/cpu.h | 44 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 42 deletions(-) diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 54989e4..b423d25 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -47,45 +47,6 @@ typedef struct LM32CPUClass { void (*parent_reset)(CPUState *cpu); } LM32CPUClass; -/** - * LM32CPU: - * @env: #CPULM32State - * - * A LatticeMico32 CPU. - */ -typedef struct LM32CPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPULM32State env; - - uint32_t revision; - uint8_t num_interrupts; - uint8_t num_breakpoints; - uint8_t num_watchpoints; - uint32_t features; -} LM32CPU; - -static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) -{ - return container_of(env, LM32CPU, env); -} - -#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(LM32CPU, env) - -#ifndef CONFIG_USER_ONLY -extern const struct VMStateDescription vmstate_lm32_cpu; -#endif - -void lm32_cpu_do_interrupt(CPUState *cpu); -bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); -void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); -hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +typedef struct LM32CPU LM32CPU; #endif diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index f220fc0..22ffa68 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -25,6 +25,7 @@ #define CPUArchState struct CPULM32State #include "qemu-common.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" struct CPULM32State; typedef struct CPULM32State CPULM32State; @@ -180,6 +181,47 @@ struct CPULM32State { }; +/** + * LM32CPU: + * @env: #CPULM32State + * + * A LatticeMico32 CPU. + */ +struct LM32CPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPULM32State env; + + uint32_t revision; + uint8_t num_interrupts; + uint8_t num_breakpoints; + uint8_t num_watchpoints; + uint32_t features; +}; + +static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) +{ + return container_of(env, LM32CPU, env); +} + +#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(LM32CPU, env) + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_lm32_cpu; +#endif + +void lm32_cpu_do_interrupt(CPUState *cpu); +bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); +void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + typedef enum { LM32_WP_DISABLED = 0, LM32_WP_READ, @@ -193,8 +235,6 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx) return (dc >> (idx+1)*2) & 0x3; } -#include "cpu-qom.h" - LM32CPU *cpu_lm32_init(const char *cpu_model); int cpu_lm32_exec(CPUState *cpu); /* you can call this signal handler from your SIGBUS and SIGSEGV