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[94.39.161.17]) by smtp.gmail.com with ESMTPSA id wr2sm2418094wjc.49.2016.03.16.03.47.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Mar 2016 03:47:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Wed, 16 Mar 2016 11:46:21 +0100 Message-Id: <1458125219-131698-12-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> References: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22a Subject: [Qemu-devel] [PATCH 11/49] target-microblaze: make cpu-qom.h not target specific X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make MicroBlazeCPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini --- target-microblaze/cpu-qom.h | 44 +------------------------------------------- target-microblaze/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 44 deletions(-) diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 34f6273..1a61db7 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -47,48 +47,6 @@ typedef struct MicroBlazeCPUClass { void (*parent_reset)(CPUState *cpu); } MicroBlazeCPUClass; -/** - * MicroBlazeCPU: - * @env: #CPUMBState - * - * A MicroBlaze CPU. - */ -typedef struct MicroBlazeCPU { - /*< private >*/ - CPUState parent_obj; - - /*< public >*/ - - /* Microblaze Configuration Settings */ - struct { - bool stackprot; - uint32_t base_vectors; - uint8_t use_fpu; - bool use_mmu; - bool dcache_writeback; - bool endi; - char *version; - uint8_t pvr; - } cfg; - - CPUMBState env; -} MicroBlazeCPU; - -static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) -{ - return container_of(env, MicroBlazeCPU, env); -} - -#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(MicroBlazeCPU, env) - -void mb_cpu_do_interrupt(CPUState *cs); -bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); -void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); -hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +typedef struct MicroBlazeCPU MicroBlazeCPU; #endif diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 2f7335e..4c4db7f 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -20,6 +20,7 @@ #define CPU_MICROBLAZE_H #include "qemu-common.h" +#include "cpu-qom.h" #define TARGET_LONG_BITS 32 @@ -274,7 +275,49 @@ struct CPUMBState { } pvr; }; -#include "cpu-qom.h" +/** + * MicroBlazeCPU: + * @env: #CPUMBState + * + * A MicroBlaze CPU. + */ +struct MicroBlazeCPU { + /*< private >*/ + CPUState parent_obj; + + /*< public >*/ + + /* Microblaze Configuration Settings */ + struct { + bool stackprot; + uint32_t base_vectors; + uint8_t use_fpu; + bool use_mmu; + bool dcache_writeback; + bool endi; + char *version; + uint8_t pvr; + } cfg; + + CPUMBState env; +}; + +static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) +{ + return container_of(env, MicroBlazeCPU, env); +} + +#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(MicroBlazeCPU, env) + +void mb_cpu_do_interrupt(CPUState *cs); +bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void mb_tcg_init(void); MicroBlazeCPU *cpu_mb_init(const char *cpu_model);