From patchwork Tue Mar 29 02:35:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 8681511 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8BA80C0554 for ; Tue, 29 Mar 2016 02:36:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B53BA201DD for ; Tue, 29 Mar 2016 02:36:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFCCD201FE for ; Tue, 29 Mar 2016 02:36:23 +0000 (UTC) Received: from localhost ([::1]:44103 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akjW3-00034y-3e for patchwork-qemu-devel@patchwork.kernel.org; Mon, 28 Mar 2016 22:36:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akjVr-00033u-QM for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1akjVn-0006cT-Sd for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:11 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:32250) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1akjVn-0006bP-Iv for qemu-devel@nongnu.org; Mon, 28 Mar 2016 22:36:07 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id D0EDE50D42FB6; Tue, 29 Mar 2016 03:36:00 +0100 (IST) Received: from BAMAIL02.ba.imgtec.org (10.20.40.28) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Tue, 29 Mar 2016 03:36:01 +0100 Received: from mipscs447.ba.imgtec.org (10.20.51.47) by bamail02.ba.imgtec.org (10.20.40.28) with Microsoft SMTP Server (TLS) id 14.3.266.1; Mon, 28 Mar 2016 19:35:58 -0700 Received: from mipscs447.ba.imgtec.org (localhost.localdomain [127.0.0.1]) by mipscs447.ba.imgtec.org (8.13.8/8.13.8) with ESMTP id u2T2ZwJ8009466; Mon, 28 Mar 2016 19:35:58 -0700 Received: (from ygk@localhost) by mipscs447.ba.imgtec.org (8.13.8/8.13.8/Submit) id u2T2ZwEm009465; Mon, 28 Mar 2016 19:35:58 -0700 From: Yongbok Kim To: Date: Mon, 28 Mar 2016 19:35:50 -0700 Message-ID: <1459218952-9408-2-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1459218952-9408-1-git-send-email-yongbok.kim@imgtec.com> References: <1459218952-9408-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Yongbok Kim , peter.maydell@linaro.org, crosthwaitepeter@gmail.com, leon.alrae@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v3 1/3] hw/mips: implement GIC Interval Timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The interval timer is similar to the CP0 Count/Compare timer within each processor. The difference is the GIC_SH_COUNTER register is global to the system so that all processors have the same time reference. To ease implementation, all VPs are having its own QEMU timer but sharing global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and GIC_SH_COUNTER. MIPS GIC Interval Timer does support upto 64 bits of Count register but in this implementation it is limited to 32 bits only. Signed-off-by: Yongbok Kim --- hw/timer/Makefile.objs | 1 + hw/timer/mips_gictimer.c | 141 ++++++++++++++++++++++++++++++++++++++ include/hw/timer/mips_gictimer.h | 46 ++++++++++++ 3 files changed, 188 insertions(+), 0 deletions(-) create mode 100644 hw/timer/mips_gictimer.c create mode 100644 include/hw/timer/mips_gictimer.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 003c14f..7ba8c23 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP) += omap_synctimer.o obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o obj-$(CONFIG_SH4) += sh_timer.o obj-$(CONFIG_DIGIC) += digic-timer.o +obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o obj-$(CONFIG_MC146818RTC) += mc146818rtc.o diff --git a/hw/timer/mips_gictimer.c b/hw/timer/mips_gictimer.c new file mode 100644 index 0000000..f1ea9ba --- /dev/null +++ b/hw/timer/mips_gictimer.c @@ -0,0 +1,141 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2016 Imagination Technologies + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/timer/mips_gictimer.h" + +#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ + +static void gic_vptimer_update(MIPSGICTimerState *gictimer, + uint32_t vp_index, uint64_t now) +{ + uint64_t next; + uint32_t wait; + + wait = gictimer->vptimers[vp_index].comparelo - gictimer->sh_counterlo - + (uint32_t)(now / TIMER_PERIOD); + next = now + (uint64_t)wait * TIMER_PERIOD; + + timer_mod(gictimer->vptimers[vp_index].qtimer, next); +} + +static void gic_vptimer_expire(MIPSGICTimerState *gictimer, uint32_t vp_index, + uint64_t now) +{ + if (gictimer->countstop) { + /* timer stopped */ + return; + } + gictimer->cb(gictimer->opaque, vp_index); + gic_vptimer_update(gictimer, vp_index, now); +} + +static void gic_vptimer_cb(void *opaque) +{ + MIPSGICTimerVPState *vptimer = opaque; + MIPSGICTimerState *gictimer = vptimer->gictimer; + gic_vptimer_expire(gictimer, vptimer->vp_index, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); +} + +uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gictimer) +{ + int i; + if (gictimer->countstop) { + return gictimer->sh_counterlo; + } else { + uint64_t now; + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + for (i = 0; i < gictimer->num_vps; i++) { + if (timer_pending(gictimer->vptimers[i].qtimer) + && timer_expired(gictimer->vptimers[i].qtimer, now)) { + /* The timer has already expired. */ + gic_vptimer_expire(gictimer, i, now); + } + } + return gictimer->sh_counterlo + (uint32_t)(now / TIMER_PERIOD); + } +} + +void mips_gictimer_store_sh_count(MIPSGICTimerState *gictimer, uint64_t count) +{ + int i; + uint64_t now; + + if (gictimer->countstop || !gictimer->vptimers[0].qtimer) { + gictimer->sh_counterlo = count; + } else { + /* Store new count register */ + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + gictimer->sh_counterlo = count - (uint32_t)(now / TIMER_PERIOD); + /* Update timer timer */ + for (i = 0; i < gictimer->num_vps; i++) { + gic_vptimer_update(gictimer, i, now); + } + } +} + +uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer, + uint32_t vp_index) +{ + return gictimer->vptimers[vp_index].comparelo; +} + +void mips_gictimer_store_vp_compare(MIPSGICTimerState *gictimer, + uint32_t vp_index, uint64_t compare) +{ + gictimer->vptimers[vp_index].comparelo = (uint32_t) compare; + gic_vptimer_update(gictimer, vp_index, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); +} + +uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gictimer) +{ + return gictimer->countstop; +} + +void mips_gictimer_start_count(MIPSGICTimerState *gictimer) +{ + gictimer->countstop = 0; + mips_gictimer_store_sh_count(gictimer, gictimer->sh_counterlo); +} + +void mips_gictimer_stop_count(MIPSGICTimerState *gictimer) +{ + int i; + + gictimer->countstop = 1; + /* Store the current value */ + gictimer->sh_counterlo += + (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD); + for (i = 0; i < gictimer->num_vps; i++) { + timer_del(gictimer->vptimers[i].qtimer); + } +} + +MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps, + MIPSGICTimerCB *cb) +{ + int i; + MIPSGICTimerState *gictimer = g_new(MIPSGICTimerState, 1); + gictimer->vptimers = g_new(MIPSGICTimerVPState, nvps); + gictimer->countstop = 1; + gictimer->num_vps = nvps; + gictimer->opaque = opaque; + gictimer->cb = cb; + for (i = 0; i < nvps; i++) { + gictimer->vptimers[i].gictimer = gictimer; + gictimer->vptimers[i].vp_index = i; + gictimer->vptimers[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &gic_vptimer_cb, + &gictimer->vptimers[i]); + } + return gictimer; +} diff --git a/include/hw/timer/mips_gictimer.h b/include/hw/timer/mips_gictimer.h new file mode 100644 index 0000000..e3ca45c --- /dev/null +++ b/include/hw/timer/mips_gictimer.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2016 Imagination Technologies + * + */ + +#ifndef _MIPS_GICTIMER_H_ +#define _MIPS_GICTIMER_H_ + +typedef struct MIPSGICTimerVPState MIPSGICTimerVPState; +typedef struct MIPSGICTimerState MIPSGICTimerState; + +typedef void MIPSGICTimerCB(void *opaque, uint32_t vp_index); + +struct MIPSGICTimerVPState { + QEMUTimer *qtimer; + uint32_t vp_index; + uint32_t comparelo; + MIPSGICTimerState *gictimer; +}; + +struct MIPSGICTimerState { + void *opaque; + uint8_t countstop; + uint32_t sh_counterlo; + int32_t num_vps; + MIPSGICTimerVPState *vptimers; + MIPSGICTimerCB *cb; +}; + +uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic); +void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count); +uint32_t mips_gictimer_get_vp_compare(MIPSGICTimerState *gictimer, + uint32_t vp_index); +void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index, + uint64_t compare); +uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic); +void mips_gictimer_start_count(MIPSGICTimerState *gic); +void mips_gictimer_stop_count(MIPSGICTimerState *gic); +MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps, + MIPSGICTimerCB *cb); + +#endif /* _MIPS_GICTIMER_H_ */