From patchwork Wed Mar 30 08:49:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 8693771 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 54B1CC0553 for ; Wed, 30 Mar 2016 08:51:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 836372034F for ; Wed, 30 Mar 2016 08:51:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C948A20274 for ; Wed, 30 Mar 2016 08:50:57 +0000 (UTC) Received: from localhost ([::1]:52517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBq5-0002qC-9D for patchwork-qemu-devel@patchwork.kernel.org; Wed, 30 Mar 2016 04:50:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpn-0002l2-Ur for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpm-0001pw-Ri for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:39 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:56195) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpm-0001ph-LU for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:38 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id E001DF47D81E4 for ; Wed, 30 Mar 2016 09:50:34 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:36 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:49:51 +0100 Message-ID: <1459327802-5102-11-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 10/21] hw/mips_malta: add CPS to Malta board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the user specifies smp > 1 and the CPU with CM GCR support, then create Coherent Processing System (which takes care of instantiating CPUs) rather than CPUs directly and connect i8259 and cbus to the pins exposed by CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use the same pin numbers as before. Signed-off-by: Leon Alrae --- hw/mips/mips_malta.c | 60 ++++++++++++++++++++++++++++++++++++++++--------- target-mips/cpu.h | 1 + target-mips/translate.c | 10 +++++++++ 3 files changed, 60 insertions(+), 11 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index cc32a44..fa769e5 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -57,6 +57,7 @@ #include "hw/empty_slot.h" #include "sysemu/kvm.h" #include "exec/semihost.h" +#include "hw/mips/cps.h" //#define DEBUG_BOARD_INIT @@ -95,6 +96,7 @@ typedef struct { typedef struct { SysBusDevice parent_obj; + MIPSCPSState *cps; qemu_irq *i8259; } MaltaState; @@ -908,19 +910,12 @@ static void main_cpu_reset(void *opaque) } } -static void create_cpu(const char *cpu_model, - qemu_irq *cbus_irq, qemu_irq *i8259_irq) +static void create_cpu_without_cps(const char *cpu_model, + qemu_irq *cbus_irq, qemu_irq *i8259_irq) { CPUMIPSState *env; MIPSCPU *cpu; int i; - if (cpu_model == NULL) { -#ifdef TARGET_MIPS64 - cpu_model = "20Kc"; -#else - cpu_model = "24Kf"; -#endif - } for (i = 0; i < smp_cpus; i++) { cpu = cpu_mips_init(cpu_model); @@ -942,6 +937,49 @@ static void create_cpu(const char *cpu_model, *cbus_irq = env->irq[4]; } +static void create_cps(MaltaState *s, const char *cpu_model, + qemu_irq *cbus_irq, qemu_irq *i8259_irq) +{ + Error *err = NULL; + s->cps = g_new0(MIPSCPSState, 1); + + object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS); + qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); + + object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err); + object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); + object_property_set_bool(OBJECT(s->cps), true, "realized", &err); + if (err != NULL) { + error_report("%s", error_get_pretty(err)); + exit(1); + } + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); + + /* FIXME: When GIC is present then we should use GIC's IRQ 3. + Until then CPS exposes CPU's IRQs thus use the default IRQ 2. */ + *i8259_irq = get_cps_irq(s->cps, 2); + *cbus_irq = NULL; +} + +static void create_cpu(MaltaState *s, const char *cpu_model, + qemu_irq *cbus_irq, qemu_irq *i8259_irq) +{ + if (cpu_model == NULL) { +#ifdef TARGET_MIPS64 + cpu_model = "20Kc"; +#else + cpu_model = "24Kf"; +#endif + } + + if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) { + create_cps(s, cpu_model, cbus_irq, i8259_irq); + } else { + create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq); + } +} + static void mips_malta_init(MachineState *machine) { @@ -994,8 +1032,8 @@ void mips_malta_init(MachineState *machine) } } - /* create CPUs */ - create_cpu(machine->cpu_model, &cbus_irq, &i8259_irq); + /* create CPU */ + create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq); /* allocate RAM */ if (ram_size > (2048u << 20)) { diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 55d3224..63fea67 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -760,6 +760,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) +bool cpu_supports_cps_smp(const char *cpu_model); /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); diff --git a/target-mips/translate.c b/target-mips/translate.c index 8191b92..a5b8805 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19977,6 +19977,16 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) return cpu; } +bool cpu_supports_cps_smp(const char *cpu_model) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; +} + void cpu_state_reset(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env);