diff mbox

target-i386: do not read/write MSR_TSC_AUX from KVM if CPUID bit is not set

Message ID 1459371583-4824-1-git-send-email-pbonzini@redhat.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paolo Bonzini March 30, 2016, 8:59 p.m. UTC
KVM does not let you read or write this MSR if the corresponding CPUID
bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
to be ignored by KVM_SET_MRSS.

One visible symptom is that s3.flat from kvm-unit-tests fails with
CPUs that do not have RDTSCP, because the SMBASE is not reset to
0x30000 after reset.

Fixes: c9b8f6b6210847b4381c5b2ee172b1c7eb9985d6
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target-i386/kvm.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Laszlo Ersek March 31, 2016, 12:56 p.m. UTC | #1
On 03/30/16 22:59, Paolo Bonzini wrote:
> KVM does not let you read or write this MSR if the corresponding CPUID
> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
> to be ignored by KVM_SET_MRSS.

typo: KVM_SET_MRSS / KVM_SET_MSRS

Thanks for fixing this.
Laszlo

> 
> One visible symptom is that s3.flat from kvm-unit-tests fails with
> CPUs that do not have RDTSCP, because the SMBASE is not reset to
> 0x30000 after reset.
> 
> Fixes: c9b8f6b6210847b4381c5b2ee172b1c7eb9985d6
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target-i386/kvm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index 87ab969..19e2d94 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -917,6 +917,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
>      if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
>          has_msr_mtrr = true;
>      }
> +    if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
> +        has_msr_tsc_aux = false;
> +    }
>  
>      return 0;
>  }
>
Peter Lieven March 31, 2016, 1:12 p.m. UTC | #2
Am 31.03.2016 um 14:56 schrieb Laszlo Ersek:
> On 03/30/16 22:59, Paolo Bonzini wrote:
>> KVM does not let you read or write this MSR if the corresponding CPUID
>> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
>> to be ignored by KVM_SET_MRSS.

Is it possible that this causes a freeze when migrating vom qemu 2.2.0 to 2.5.1?

Thanks,
Peter
Paolo Bonzini March 31, 2016, 1:23 p.m. UTC | #3
On 31/03/2016 15:12, Peter Lieven wrote:
>>
>>> KVM does not let you read or write this MSR if the corresponding CPUID
>>> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
>>> to be ignored by KVM_SET_MRSS.
> 
> Is it possible that this causes a freeze when migrating vom qemu 2.2.0
> to 2.5.1?

I wouldn't exclude it if the CPU model is Westmere or earlier.

Paolo
Peter Lieven March 31, 2016, 3:38 p.m. UTC | #4
> Am 31.03.2016 um 15:23 schrieb Paolo Bonzini <pbonzini@redhat.com>:
> 
> 
> 
>> On 31/03/2016 15:12, Peter Lieven wrote:
>>>> 
>>>> KVM does not let you read or write this MSR if the corresponding CPUID
>>>> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
>>>> to be ignored by KVM_SET_MRSS.
>> 
>> Is it possible that this causes a freeze when migrating vom qemu 2.2.0
>> to 2.5.1?
> 
> I wouldn't exclude it if the CPU model is Westmere or earlier.

the Host CPU or the Emulated CPU?

We emulate Westmere and have also some old blades with Westmere CPUs.

anyway, i give this a try.

Michael, this should have gone into 2.5.1 i think...

Thanks,
Peter
Eduardo Habkost March 31, 2016, 4:26 p.m. UTC | #5
On Wed, Mar 30, 2016 at 10:59:42PM +0200, Paolo Bonzini wrote:
> KVM does not let you read or write this MSR if the corresponding CPUID
> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
> to be ignored by KVM_SET_MRSS.
> 
> One visible symptom is that s3.flat from kvm-unit-tests fails with
> CPUs that do not have RDTSCP, because the SMBASE is not reset to
> 0x30000 after reset.
> 
> Fixes: c9b8f6b6210847b4381c5b2ee172b1c7eb9985d6
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Paolo Bonzini March 31, 2016, 4:52 p.m. UTC | #6
On 31/03/2016 17:38, Peter Lieven wrote:
> 
> 
>> Am 31.03.2016 um 15:23 schrieb Paolo Bonzini <pbonzini@redhat.com>:
>>
>>
>>
>>> On 31/03/2016 15:12, Peter Lieven wrote:
>>>>>
>>>>> KVM does not let you read or write this MSR if the corresponding CPUID
>>>>> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
>>>>> to be ignored by KVM_SET_MRSS.
>>>
>>> Is it possible that this causes a freeze when migrating vom qemu 2.2.0
>>> to 2.5.1?
>>
>> I wouldn't exclude it if the CPU model is Westmere or earlier.
> 
> the Host CPU or the Emulated CPU?

The guest.

Paolo

> We emulate Westmere and have also some old blades with Westmere CPUs.
> 
> anyway, i give this a try.
> 
> Michael, this should have gone into 2.5.1 i think...
> 
> Thanks,
> Peter
> 
>
Peter Lieven March 31, 2016, 7:21 p.m. UTC | #7
Am 31.03.2016 um 18:52 schrieb Paolo Bonzini:
>
> On 31/03/2016 17:38, Peter Lieven wrote:
>>
>>> Am 31.03.2016 um 15:23 schrieb Paolo Bonzini <pbonzini@redhat.com>:
>>>
>>>
>>>
>>>> On 31/03/2016 15:12, Peter Lieven wrote:
>>>>>> KVM does not let you read or write this MSR if the corresponding CPUID
>>>>>> bit is not set.  This in turn causes MSRs that come after MSR_TSC_AUX
>>>>>> to be ignored by KVM_SET_MRSS.
>>>> Is it possible that this causes a freeze when migrating vom qemu 2.2.0
>>>> to 2.5.1?
>>> I wouldn't exclude it if the CPU model is Westmere or earlier.
>> the Host CPU or the Emulated CPU?
> The guest.

I can confirm this seems to fix the migration for emulated Westmere CPUs. Regardless if its a 2.2.0 -> 2.5.1 or 2.5.1 -> 2.5.1
migration.

Peter
diff mbox

Patch

diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 87ab969..19e2d94 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -917,6 +917,9 @@  int kvm_arch_init_vcpu(CPUState *cs)
     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
         has_msr_mtrr = true;
     }
+    if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
+        has_msr_tsc_aux = false;
+    }
 
     return 0;
 }