From patchwork Fri Apr 1 18:39:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Kiarie X-Patchwork-Id: 8727021 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E22DB9F38C for ; Fri, 1 Apr 2016 18:41:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC40E203A1 for ; Fri, 1 Apr 2016 18:41:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C7CE2034E for ; Fri, 1 Apr 2016 18:41:29 +0000 (UTC) Received: from localhost ([::1]:45880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am40e-0007C6-W9 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 01 Apr 2016 14:41:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am40R-0007Bs-3J for qemu-devel@nongnu.org; Fri, 01 Apr 2016 14:41:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1am40N-0007is-Uk for qemu-devel@nongnu.org; Fri, 01 Apr 2016 14:41:15 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am40N-0007ii-KJ for qemu-devel@nongnu.org; Fri, 01 Apr 2016 14:41:11 -0400 Received: by mail-wm0-x242.google.com with SMTP id 20so334857wmh.3 for ; Fri, 01 Apr 2016 11:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kxgHL/znnS44y9foXBoW8hJMyr5YfyhMf/u0zHlvgws=; b=oG4H18QBZaxxT7fXH3exzrWjPWNz52QRqRfF/GtxLiTytLXeQnNTkpxEY7wV5bS/Sp cl16oBNnVujHf2ALbotw7XyNO6cKL916BWNHhY+46gtyT3xjFy+AaVGYepZKy+aAquVr 2kofymwJLk13dbWPrKCZ+ufXX2Ec/XZWVsNKxGQSdE0AmiZFt295chYMt1JpXm2PA0Op fWHj5YxYdb8m6lNkE0lwR6c29tvw+XbTRu1vAnmpnC1orZH/B+kXTirpzr2W3Nd2Le8o XyD5jydipW2mr/7KJTfink9r4MxZFqShq040w31IaSAHFfJsbBAkW16xEm/XpgkBUD9v oilg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kxgHL/znnS44y9foXBoW8hJMyr5YfyhMf/u0zHlvgws=; b=JtX+o5hbIycGdZoOa61jxX/y7wqOa8OkGz/2eFeY9s8KM7aF8r9EXhRIYlZRDMxJGx YLtHA4XbekuE8we7b53VzK8kq0/xK6zfQ7lCzk/Th+ErV/7M1HRHWjxWJGN3q5U5Mngm Mp6sOtXzkBkpTWv2vAuz/xXZROYNHHqJFYWwinv7UVY8tNnfDamXN8SmF6Y2NsZ2pTOE qOhS+91janyCL75BZahn7Eg0b36ZsbjDbvh8wMpQffHp1gz3QaEGpAM1i5bjYYu1aiJG nkUjSIk6/hejUntzdSdYaR9wugXutF3smNsJ7aMXueYWZt/pJyFlV46tdnurDKHMBpdE mdMw== X-Gm-Message-State: AD7BkJJRSzkXh4Iq38Ii3v4l3vm4XyrwqYAMCMM9wFCW7RkFYHpmezaPNprKTf7kBRqSIw== X-Received: by 10.28.156.196 with SMTP id f187mr201713wme.23.1459536068785; Fri, 01 Apr 2016 11:41:08 -0700 (PDT) Received: from debian.flybox.orange ([154.122.176.211]) by smtp.googlemail.com with ESMTPSA id w184sm233275wmb.1.2016.04.01.11.41.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Apr 2016 11:41:08 -0700 (PDT) From: David Kiarie To: qemu-devel@nongnu.org Date: Fri, 1 Apr 2016 21:39:52 +0300 Message-Id: <1459535994-18523-3-git-send-email-davidkiarie4@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1459535994-18523-1-git-send-email-davidkiarie4@gmail.com> References: <1459535994-18523-1-git-send-email-davidkiarie4@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Cc: marcel@redhat.com, valentine.sinitsyn@gmail.com, David Kiarie , jan.kizska@web.de, mst@redhat.com Subject: [Qemu-devel] [V8 2/4] hw/i386: ACPI table for AMD IOMMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add IVRS table for AMD IOMMU. Generate IVRS or DMAR depending on emulated IOMMU Signed-off-by: David Kiarie --- hw/i386/acpi-build.c | 98 ++++++++++++++++++++++++++++++++++++++----- include/hw/acpi/acpi-defs.h | 55 ++++++++++++++++++++++++ include/hw/i386/intel_iommu.h | 1 + 3 files changed, 143 insertions(+), 11 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 35180ef..a54a22c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -52,6 +52,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci-host/q35.h" #include "hw/i386/intel_iommu.h" +#include "hw/i386/amd_iommu.h" #include "hw/timer/hpet.h" #include "hw/acpi/aml-build.h" @@ -118,6 +119,12 @@ typedef struct AcpiBuildPciBusHotplugState { bool pcihp_bridge_en; } AcpiBuildPciBusHotplugState; +typedef enum iommu_type { + TYPE_AMD, + TYPE_INTEL, + TYPE_NONE +} iommu_type; + static void acpi_get_pm_info(AcpiPmInfo *pm) { Object *piix = piix4_pm_find(); @@ -2588,6 +2595,78 @@ build_dmar_q35(GArray *table_data, GArray *linker) "DMAR", table_data->len - dmar_start, 1, NULL, NULL); } +static void +build_amd_iommu(GArray *table_data, GArray *linker) +{ + int iommu_start = table_data->len; + bool iommu_ambig; + + AcpiAMDIOMMUIVRS *ivrs; + AcpiAMDIOMMUHardwareUnit *iommu; + + /* IVRS definition */ + ivrs = acpi_data_push(table_data, sizeof(*ivrs)); + ivrs->revision = cpu_to_le16(ACPI_IOMMU_IVRS_TYPE); + ivrs->length = cpu_to_le16((sizeof(*ivrs) + sizeof(*iommu))); + ivrs->v_common_info = cpu_to_le64(AMD_IOMMU_HOST_ADDRESS_WIDTH << 8); + + AMDIOMMUState *s = (AMDIOMMUState *)object_resolve_path_type("", + TYPE_AMD_IOMMU_DEVICE, &iommu_ambig); + + /* IVDB definition - type 10h */ + iommu = acpi_data_push(table_data, sizeof(*iommu)); + if (!iommu_ambig) { + iommu->type = cpu_to_le16(0x10); + /* IVHD flags */ + iommu->flags = cpu_to_le16(iommu->flags); + iommu->flags = cpu_to_le16(IVHD_HT_TUNEN | IVHD_PPRSUP | IVHD_IOTLBSUP + | IVHD_PREFSUP); + iommu->length = cpu_to_le16(sizeof(*iommu)); + iommu->device_id = cpu_to_le16(PCI_DEVICE_ID_RD890_IOMMU); + iommu->capability_offset = cpu_to_le16(s->capab_offset); + iommu->mmio_base = cpu_to_le64(s->mmio.addr); + iommu->pci_segment = 0; + iommu->interrupt_info = 0; + /* EFR features */ + iommu->efr_register = cpu_to_le64(IVHD_EFR_GTSUP | IVHD_EFR_HATS + | IVHD_EFR_GATS); + iommu->efr_register = cpu_to_le64(iommu->efr_register); + /* device entries */ + memset(iommu->dev_entries, 0, 20); + /* Add device flags here + * This is are 4-byte device entries currently reporting the range of + * devices 00h - ffffh; all devices + * + * Device setting affecting all devices should be made here + * + * Refer to + * (http://developer.amd.com/wordpress/media/2012/10/488821.pdf) + * 5.2.2.1 + */ + iommu->dev_entries[12] = 3; + iommu->dev_entries[16] = 4; + iommu->dev_entries[17] = 0xff; + iommu->dev_entries[18] = 0xff; + } + + build_header(linker, table_data, (void *)(table_data->data + iommu_start), + "IVRS", table_data->len - iommu_start, 1, NULL, NULL); +} + +static iommu_type has_iommu(void) +{ + bool ambiguous; + + if (object_resolve_path_type("", TYPE_AMD_IOMMU_DEVICE, &ambiguous) + && !ambiguous) + return TYPE_AMD; + else if (object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, &ambiguous) + && !ambiguous) + return TYPE_INTEL; + else + return TYPE_NONE; +} + static GArray * build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt) { @@ -2646,16 +2725,6 @@ static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) return true; } -static bool acpi_has_iommu(void) -{ - bool ambiguous; - Object *intel_iommu; - - intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, - &ambiguous); - return intel_iommu && !ambiguous; -} - static void acpi_build(AcpiBuildTables *tables, MachineState *machine) { @@ -2668,6 +2737,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) AcpiMcfgInfo mcfg; PcPciInfo pci; uint8_t *u; + iommu_type type = has_iommu(); size_t aml_len = 0; GArray *tables_blob = tables->table_data; AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; @@ -2733,7 +2803,13 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) acpi_add_table(table_offsets, tables_blob); build_mcfg_q35(tables_blob, tables->linker, &mcfg); } - if (acpi_has_iommu()) { + + if (type == TYPE_AMD) { + acpi_add_table(table_offsets, tables_blob); + build_amd_iommu(tables_blob, tables->linker); + } + + if (type == TYPE_INTEL) { acpi_add_table(table_offsets, tables_blob); build_dmar_q35(tables_blob, tables->linker); } diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index c7a03d4..a161358 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -570,4 +570,59 @@ typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; /* Masks for Flags field above */ #define ACPI_DMAR_INCLUDE_PCI_ALL 1 +/* IVRS constants */ +#define ACPI_IOMMU_HARDWAREUNIT_TYPE 0x10 +#define ACPI_IOMMU_IVRS_TYPE 0x1 +#define AMD_IOMMU_HOST_ADDRESS_WIDTH 39UL + +/* AMD IOMMU IVRS table */ +struct AcpiAMDIOMMUIVRS { + ACPI_TABLE_HEADER_DEF + uint32_t v_common_info; /* common virtualization information */ + uint64_t reserved; /* reserved */ +} QEMU_PACKED; +typedef struct AcpiAMDIOMMUIVRS AcpiAMDIOMMUIVRS; + +/* flags in the IVHD headers */ +#define IVHD_HT_TUNEN (1UL << 0) +#define IVHD_PASS_PW (1UL << 1) +#define IVHD_RESPASS_PW (1UL << 2) +#define IVHD_ISOC (1UL << 3) +#define IVHD_IOTLBSUP (1UL << 4) +#define IVHD_COHERENT (1UL << 5) +#define IVHD_PREFSUP (1UL << 6) +#define IVHD_PPRSUP (1UL << 7) + +/* features in the IVHD headers */ +#define IVHD_EFR_HATS 48 +#define IVHD_EFR_GATS 48 +#define IVHD_EFR_MSI_NUM +#define IVHD_EFR_PNBANKS +#define IVHD_EFR_PNCOUNTERS +#define IVHD_EFR_PASMAX +#define IVHD_EFR_HESUP (1UL << 7) +#define IVHD_EFR_GASUP (1UL << 6) +#define IVHD_EFR_IASUP (1UL << 5) +#define IVHD_EFR_GLXSUP (3UL << 3) +#define IVHD_EFR_GTSUP (1UL << 2) +#define IVHD_EFR_NXSUP (1UL << 1) +#define IVHD_EFR_XTSUP (1UL << 0) + +/* IVDB type 10h */ +struct AcpiAMDIOMMUHardwareUnit { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint64_t mmio_base; + uint16_t pci_segment; + uint16_t interrupt_info; + uint32_t features; + uint64_t efr_register; + uint64_t reserved; + uint8_t dev_entries[20]; +} QEMU_PACKED; +typedef struct AcpiAMDIOMMUHardwareUnit AcpiAMDIOMMUHardwareUnit; + #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index b024ffa..7e511e1 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -24,6 +24,7 @@ #include "hw/qdev.h" #include "sysemu/dma.h" +#define INTEL_IOMMU_STR "intel" #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" #define INTEL_IOMMU_DEVICE(obj) \ OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)