diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index f5d9b9f..e7de30e 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -40,6 +40,163 @@
 #define XTENSA_CPU_GET_CLASS(obj) \
     OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU)
 
+enum {
+    /* Additional instructions */
+    XTENSA_OPTION_CODE_DENSITY,
+    XTENSA_OPTION_LOOP,
+    XTENSA_OPTION_EXTENDED_L32R,
+    XTENSA_OPTION_16_BIT_IMUL,
+    XTENSA_OPTION_32_BIT_IMUL,
+    XTENSA_OPTION_32_BIT_IMUL_HIGH,
+    XTENSA_OPTION_32_BIT_IDIV,
+    XTENSA_OPTION_MAC16,
+    XTENSA_OPTION_MISC_OP_NSA,
+    XTENSA_OPTION_MISC_OP_MINMAX,
+    XTENSA_OPTION_MISC_OP_SEXT,
+    XTENSA_OPTION_MISC_OP_CLAMPS,
+    XTENSA_OPTION_COPROCESSOR,
+    XTENSA_OPTION_BOOLEAN,
+    XTENSA_OPTION_FP_COPROCESSOR,
+    XTENSA_OPTION_MP_SYNCHRO,
+    XTENSA_OPTION_CONDITIONAL_STORE,
+    XTENSA_OPTION_ATOMCTL,
+    XTENSA_OPTION_DEPBITS,
+
+    /* Interrupts and exceptions */
+    XTENSA_OPTION_EXCEPTION,
+    XTENSA_OPTION_RELOCATABLE_VECTOR,
+    XTENSA_OPTION_UNALIGNED_EXCEPTION,
+    XTENSA_OPTION_INTERRUPT,
+    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
+    XTENSA_OPTION_TIMER_INTERRUPT,
+
+    /* Local memory */
+    XTENSA_OPTION_ICACHE,
+    XTENSA_OPTION_ICACHE_TEST,
+    XTENSA_OPTION_ICACHE_INDEX_LOCK,
+    XTENSA_OPTION_DCACHE,
+    XTENSA_OPTION_DCACHE_TEST,
+    XTENSA_OPTION_DCACHE_INDEX_LOCK,
+    XTENSA_OPTION_IRAM,
+    XTENSA_OPTION_IROM,
+    XTENSA_OPTION_DRAM,
+    XTENSA_OPTION_DROM,
+    XTENSA_OPTION_XLMI,
+    XTENSA_OPTION_HW_ALIGNMENT,
+    XTENSA_OPTION_MEMORY_ECC_PARITY,
+
+    /* Memory protection and translation */
+    XTENSA_OPTION_REGION_PROTECTION,
+    XTENSA_OPTION_REGION_TRANSLATION,
+    XTENSA_OPTION_MMU,
+    XTENSA_OPTION_CACHEATTR,
+
+    /* Other */
+    XTENSA_OPTION_WINDOWED_REGISTER,
+    XTENSA_OPTION_PROCESSOR_INTERFACE,
+    XTENSA_OPTION_MISC_SR,
+    XTENSA_OPTION_THREAD_POINTER,
+    XTENSA_OPTION_PROCESSOR_ID,
+    XTENSA_OPTION_DEBUG,
+    XTENSA_OPTION_TRACE_PORT,
+};
+
+#define MAX_NAREG 64
+#define MAX_NINTERRUPT 32
+#define MAX_NLEVEL 6
+#define MAX_NNMI 1
+#define MAX_NCCOMPARE 3
+#define MAX_TLB_WAY_SIZE 8
+#define MAX_NDBREAK 2
+
+enum {
+    /* Static vectors */
+    EXC_RESET,
+    EXC_MEMORY_ERROR,
+
+    /* Dynamic vectors */
+    EXC_WINDOW_OVERFLOW4,
+    EXC_WINDOW_UNDERFLOW4,
+    EXC_WINDOW_OVERFLOW8,
+    EXC_WINDOW_UNDERFLOW8,
+    EXC_WINDOW_OVERFLOW12,
+    EXC_WINDOW_UNDERFLOW12,
+    EXC_IRQ,
+    EXC_KERNEL,
+    EXC_USER,
+    EXC_DOUBLE,
+    EXC_DEBUG,
+    EXC_MAX
+};
+
+typedef enum {
+    INTTYPE_LEVEL,
+    INTTYPE_EDGE,
+    INTTYPE_NMI,
+    INTTYPE_SOFTWARE,
+    INTTYPE_TIMER,
+    INTTYPE_DEBUG,
+    INTTYPE_WRITE_ERR,
+    INTTYPE_PROFILING,
+    INTTYPE_MAX
+} interrupt_type;
+
+typedef struct xtensa_tlb {
+    unsigned nways;
+    const unsigned way_size[10];
+    bool varway56;
+    unsigned nrefillentries;
+} xtensa_tlb;
+
+typedef struct XtensaGdbReg {
+    int targno;
+    int type;
+    int group;
+    unsigned size;
+} XtensaGdbReg;
+
+typedef struct XtensaGdbRegmap {
+    int num_regs;
+    int num_core_regs;
+    /* PC + a + ar + sr + ur */
+    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
+} XtensaGdbRegmap;
+
+typedef struct XtensaConfig {
+    const char *name;
+    uint64_t options;
+    XtensaGdbRegmap gdb_regmap;
+    unsigned nareg;
+    int excm_level;
+    int ndepc;
+    uint32_t vecbase;
+    uint32_t exception_vector[EXC_MAX];
+    unsigned ninterrupt;
+    unsigned nlevel;
+    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
+    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
+    uint32_t inttype_mask[INTTYPE_MAX];
+    struct {
+        uint32_t level;
+        interrupt_type inttype;
+    } interrupt[MAX_NINTERRUPT];
+    unsigned nccompare;
+    uint32_t timerint[MAX_NCCOMPARE];
+    unsigned nextint;
+    unsigned extint[MAX_NINTERRUPT];
+
+    unsigned debug_level;
+    unsigned nibreak;
+    unsigned ndbreak;
+
+    uint32_t configid[2];
+
+    uint32_t clock_freq_khz;
+
+    xtensa_tlb itlb;
+    xtensa_tlb dtlb;
+} XtensaConfig;
+
 /**
  * XtensaCPUClass:
  * @parent_realize: The parent class' realize handler.
@@ -59,40 +216,6 @@ typedef struct XtensaCPUClass {
     const XtensaConfig *config;
 } XtensaCPUClass;
 
-/**
- * XtensaCPU:
- * @env: #CPUXtensaState
- *
- * An Xtensa CPU.
- */
-typedef struct XtensaCPU {
-    /*< private >*/
-    CPUState parent_obj;
-    /*< public >*/
-
-    CPUXtensaState env;
-} XtensaCPU;
-
-static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
-{
-    return container_of(env, XtensaCPU, env);
-}
-
-#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
-
-#define ENV_OFFSET offsetof(XtensaCPU, env)
-
-void xtensa_cpu_do_interrupt(CPUState *cpu);
-bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
-void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
-                                     bool is_write, bool is_exec, int opaque,
-                                     unsigned size);
-void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
-                           fprintf_function cpu_fprintf, int flags);
-hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
-int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
-                                    int is_write, int is_user, uintptr_t retaddr);
+typedef struct XtensaCPU XtensaCPU;
 
 #endif
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index d0bd9da..b1958f0 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -34,6 +34,7 @@
 #define CPUArchState struct CPUXtensaState
 
 #include "qemu-common.h"
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat.h"
 
@@ -44,67 +45,6 @@
 #define TARGET_PAGE_BITS 12
 
 enum {
-    /* Additional instructions */
-    XTENSA_OPTION_CODE_DENSITY,
-    XTENSA_OPTION_LOOP,
-    XTENSA_OPTION_EXTENDED_L32R,
-    XTENSA_OPTION_16_BIT_IMUL,
-    XTENSA_OPTION_32_BIT_IMUL,
-    XTENSA_OPTION_32_BIT_IMUL_HIGH,
-    XTENSA_OPTION_32_BIT_IDIV,
-    XTENSA_OPTION_MAC16,
-    XTENSA_OPTION_MISC_OP_NSA,
-    XTENSA_OPTION_MISC_OP_MINMAX,
-    XTENSA_OPTION_MISC_OP_SEXT,
-    XTENSA_OPTION_MISC_OP_CLAMPS,
-    XTENSA_OPTION_COPROCESSOR,
-    XTENSA_OPTION_BOOLEAN,
-    XTENSA_OPTION_FP_COPROCESSOR,
-    XTENSA_OPTION_MP_SYNCHRO,
-    XTENSA_OPTION_CONDITIONAL_STORE,
-    XTENSA_OPTION_ATOMCTL,
-    XTENSA_OPTION_DEPBITS,
-
-    /* Interrupts and exceptions */
-    XTENSA_OPTION_EXCEPTION,
-    XTENSA_OPTION_RELOCATABLE_VECTOR,
-    XTENSA_OPTION_UNALIGNED_EXCEPTION,
-    XTENSA_OPTION_INTERRUPT,
-    XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
-    XTENSA_OPTION_TIMER_INTERRUPT,
-
-    /* Local memory */
-    XTENSA_OPTION_ICACHE,
-    XTENSA_OPTION_ICACHE_TEST,
-    XTENSA_OPTION_ICACHE_INDEX_LOCK,
-    XTENSA_OPTION_DCACHE,
-    XTENSA_OPTION_DCACHE_TEST,
-    XTENSA_OPTION_DCACHE_INDEX_LOCK,
-    XTENSA_OPTION_IRAM,
-    XTENSA_OPTION_IROM,
-    XTENSA_OPTION_DRAM,
-    XTENSA_OPTION_DROM,
-    XTENSA_OPTION_XLMI,
-    XTENSA_OPTION_HW_ALIGNMENT,
-    XTENSA_OPTION_MEMORY_ECC_PARITY,
-
-    /* Memory protection and translation */
-    XTENSA_OPTION_REGION_PROTECTION,
-    XTENSA_OPTION_REGION_TRANSLATION,
-    XTENSA_OPTION_MMU,
-    XTENSA_OPTION_CACHEATTR,
-
-    /* Other */
-    XTENSA_OPTION_WINDOWED_REGISTER,
-    XTENSA_OPTION_PROCESSOR_INTERFACE,
-    XTENSA_OPTION_MISC_SR,
-    XTENSA_OPTION_THREAD_POINTER,
-    XTENSA_OPTION_PROCESSOR_ID,
-    XTENSA_OPTION_DEBUG,
-    XTENSA_OPTION_TRACE_PORT,
-};
-
-enum {
     THREADPTR = 231,
     FCR = 232,
     FSR = 233,
@@ -188,14 +128,6 @@ enum {
 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 #define DBREAKC_MASK 0x3f
 
-#define MAX_NAREG 64
-#define MAX_NINTERRUPT 32
-#define MAX_NLEVEL 6
-#define MAX_NNMI 1
-#define MAX_NCCOMPARE 3
-#define MAX_TLB_WAY_SIZE 8
-#define MAX_NDBREAK 2
-
 #define REGION_PAGE_MASK 0xe0000000
 
 #define PAGE_CACHE_MASK    0x700
@@ -207,26 +139,6 @@ enum {
 #define PAGE_CACHE_ISOLATE 0x600
 
 enum {
-    /* Static vectors */
-    EXC_RESET,
-    EXC_MEMORY_ERROR,
-
-    /* Dynamic vectors */
-    EXC_WINDOW_OVERFLOW4,
-    EXC_WINDOW_UNDERFLOW4,
-    EXC_WINDOW_OVERFLOW8,
-    EXC_WINDOW_UNDERFLOW8,
-    EXC_WINDOW_OVERFLOW12,
-    EXC_WINDOW_UNDERFLOW12,
-    EXC_IRQ,
-    EXC_KERNEL,
-    EXC_USER,
-    EXC_DOUBLE,
-    EXC_DEBUG,
-    EXC_MAX
-};
-
-enum {
     ILLEGAL_INSTRUCTION_CAUSE = 0,
     SYSCALL_CAUSE,
     INSTRUCTION_FETCH_ERROR_CAUSE,
@@ -255,18 +167,6 @@ enum {
     COPROCESSOR0_DISABLED = 32,
 };
 
-typedef enum {
-    INTTYPE_LEVEL,
-    INTTYPE_EDGE,
-    INTTYPE_NMI,
-    INTTYPE_SOFTWARE,
-    INTTYPE_TIMER,
-    INTTYPE_DEBUG,
-    INTTYPE_WRITE_ERR,
-    INTTYPE_PROFILING,
-    INTTYPE_MAX
-} interrupt_type;
-
 typedef struct xtensa_tlb_entry {
     uint32_t vaddr;
     uint32_t paddr;
@@ -275,62 +175,6 @@ typedef struct xtensa_tlb_entry {
     bool variable;
 } xtensa_tlb_entry;
 
-typedef struct xtensa_tlb {
-    unsigned nways;
-    const unsigned way_size[10];
-    bool varway56;
-    unsigned nrefillentries;
-} xtensa_tlb;
-
-typedef struct XtensaGdbReg {
-    int targno;
-    int type;
-    int group;
-    unsigned size;
-} XtensaGdbReg;
-
-typedef struct XtensaGdbRegmap {
-    int num_regs;
-    int num_core_regs;
-    /* PC + a + ar + sr + ur */
-    XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
-} XtensaGdbRegmap;
-
-typedef struct XtensaConfig {
-    const char *name;
-    uint64_t options;
-    XtensaGdbRegmap gdb_regmap;
-    unsigned nareg;
-    int excm_level;
-    int ndepc;
-    uint32_t vecbase;
-    uint32_t exception_vector[EXC_MAX];
-    unsigned ninterrupt;
-    unsigned nlevel;
-    uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
-    uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
-    uint32_t inttype_mask[INTTYPE_MAX];
-    struct {
-        uint32_t level;
-        interrupt_type inttype;
-    } interrupt[MAX_NINTERRUPT];
-    unsigned nccompare;
-    uint32_t timerint[MAX_NCCOMPARE];
-    unsigned nextint;
-    unsigned extint[MAX_NINTERRUPT];
-
-    unsigned debug_level;
-    unsigned nibreak;
-    unsigned ndbreak;
-
-    uint32_t configid[2];
-
-    uint32_t clock_freq_khz;
-
-    xtensa_tlb itlb;
-    xtensa_tlb dtlb;
-} XtensaConfig;
-
 typedef struct XtensaConfigList {
     const XtensaConfig *config;
     struct XtensaConfigList *next;
@@ -379,7 +223,41 @@ typedef struct CPUXtensaState {
     CPU_COMMON
 } CPUXtensaState;
 
-#include "cpu-qom.h"
+/**
+ * XtensaCPU:
+ * @env: #CPUXtensaState
+ *
+ * An Xtensa CPU.
+ */
+struct XtensaCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    /*< public >*/
+
+    CPUXtensaState env;
+};
+
+static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
+{
+    return container_of(env, XtensaCPU, env);
+}
+
+#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(XtensaCPU, env)
+
+void xtensa_cpu_do_interrupt(CPUState *cpu);
+bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
+void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
+                                     bool is_write, bool is_exec, int opaque,
+                                     unsigned size);
+void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
+                           fprintf_function cpu_fprintf, int flags);
+hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+                                    int is_write, int is_user, uintptr_t retaddr);
 
 #define cpu_exec cpu_xtensa_exec
 #define cpu_signal_handler cpu_xtensa_signal_handler
