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[94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:34 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 8 Apr 2016 22:28:41 +0200 Message-Id: <1460147350-7601-22-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 21/50] arm: include cpu-qom.h in files that require ARMCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This will keep things working when cpu.h will not be included indirectly almost everywhere (either directly or through qemu-common.h). Signed-off-by: Paolo Bonzini --- hw/arm/stm32f205_soc.c | 1 - hw/arm/strongarm.h | 1 + include/hw/arm/arm.h | 2 +- include/hw/arm/exynos4210.h | 1 + include/hw/arm/omap.h | 1 + include/hw/arm/pxa.h | 1 + 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index a5ea1e2..9c1dafb 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" #include "hw/arm/arm.h" #include "exec/address-spaces.h" #include "hw/arm/stm32f205_soc.h" diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h index 2893f94..cd32bbd 100644 --- a/hw/arm/strongarm.h +++ b/hw/arm/strongarm.h @@ -2,6 +2,7 @@ #define _STRONGARM_H #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #define SA_CS0 0x00000000 #define SA_CS1 0x08000000 diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index b2517f9..8b49a98 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -12,9 +12,9 @@ #define ARM_MISC_H 1 #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #include "hw/irq.h" #include "qemu/notify.h" -#include "cpu.h" typedef enum { ARM_ENDIANNESS_UNKNOWN = 0, diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 5c1820f..b6d929d 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -28,6 +28,7 @@ #include "qemu-common.h" #include "exec/memory.h" +#include "target-arm/cpu-qom.h" #define EXYNOS4210_NCPUS 2 diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 0ad5fb8..f026c8d 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -20,6 +20,7 @@ #include "exec/memory.h" # define hw_omap_h "omap.h" #include "hw/irq.h" +#include "target-arm/cpu-qom.h" # define OMAP_EMIFS_BASE 0x00000000 # define OMAP2_Q0_BASE 0x00000000 diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 259b852..074feac 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -10,6 +10,7 @@ # define PXA_H "pxa.h" #include "exec/memory.h" +#include "target-arm/cpu-qom.h" /* Interrupt numbers */ # define PXA2XX_PIC_SSP3 0