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[94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:38 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 8 Apr 2016 22:28:45 +0200 Message-Id: <1460147350-7601-26-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 25/50] mips: use MIPSCPU instead of CPUMIPSState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This changes a cpu.h dependency into a cpu-qom.h dependency. Signed-off-by: Paolo Bonzini --- hw/mips/cps.c | 7 ++++--- hw/mips/cputimer.c | 4 +++- hw/mips/mips_fulong2e.c | 4 ++-- hw/mips/mips_int.c | 3 ++- hw/mips/mips_jazz.c | 4 ++-- hw/mips/mips_malta.c | 5 ++--- hw/mips/mips_mipssim.c | 4 ++-- hw/mips/mips_r4k.c | 4 ++-- include/hw/mips/cpudevs.h | 7 +++++-- 9 files changed, 24 insertions(+), 18 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 1bafbbb..61208f8 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -81,11 +81,12 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) error_setg(errp, "%s: CPU initialization failed\n", __func__); return; } - env = &cpu->env; /* Init internal devices */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); + + env = &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c index efb227d..8a166b3 100644 --- a/hw/mips/cputimer.c +++ b/hw/mips/cputimer.c @@ -151,8 +151,10 @@ static void mips_timer_cb (void *opaque) env->CP0_Count--; } -void cpu_mips_clock_init (CPUMIPSState *env) +void cpu_mips_clock_init (MIPSCPU *cpu) { + CPUMIPSState *env = &cpu->env; + /* * If we're in KVM mode, don't create the periodic timer, that is handled in * kernel. diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index bdb716e7..889cdc7 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -334,8 +334,8 @@ static void mips_fulong2e_init(MachineState *machine) } /* Init internal devices */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); /* North bridge, Bonito --> IP2 */ pci_bus = bonito_init((qemu_irq *)&(env->irq[2])); diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 59081f9..48192d2 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -58,8 +58,9 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) } } -void cpu_mips_irq_init_cpu(CPUMIPSState *env) +void cpu_mips_irq_init_cpu(MIPSCPU *cpu) { + CPUMIPSState *env = &cpu->env; qemu_irq *qi; int i; diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index ac7c641..73f6c9f 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -201,8 +201,8 @@ static void mips_jazz_init(MachineState *machine, } /* Init CPU internal devices */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); /* Chipset */ rc4030 = rc4030_init(&dmas, &rc4030_dma_mr); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index fa769e5..5c8ba44 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -923,11 +923,10 @@ static void create_cpu_without_cps(const char *cpu_model, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - env = &cpu->env; /* Init internal devices */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); qemu_register_reset(main_cpu_reset, cpu); } diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index a2c2a16..1b91195 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -216,8 +216,8 @@ mips_mipssim_init(MachineState *machine) } /* Init CPU internal devices. */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); /* Register 64 KB of ISA IO space at 0x1fd00000. */ memory_region_init_alias(isa, NULL, "isa_mmio", diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 21aca98..16a59c7 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -267,8 +267,8 @@ void mips_r4k_init(MachineState *machine) } /* Init CPU internal devices */ - cpu_mips_irq_init_cpu(env); - cpu_mips_clock_init(env); + cpu_mips_irq_init_cpu(cpu); + cpu_mips_clock_init(cpu); /* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */ memory_region_init_alias(isa_io, NULL, "isa-io", diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index b2626f2..8673daa 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -1,5 +1,8 @@ #ifndef HW_MIPS_CPUDEVS_H #define HW_MIPS_CPUDEVS_H + +#include "target-mips/cpu-qom.h" + /* Definitions for MIPS CPU internal devices. */ /* mips_addr.c */ @@ -9,9 +12,9 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); /* mips_int.c */ -void cpu_mips_irq_init_cpu(CPUMIPSState *env); +void cpu_mips_irq_init_cpu(MIPSCPU *cpu); /* mips_timer.c */ -void cpu_mips_clock_init(CPUMIPSState *); +void cpu_mips_clock_init(MIPSCPU *cpu); #endif