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[94.39.141.76]) by smtp.gmail.com with ESMTPSA id w10sm3849168wjz.9.2016.04.08.13.29.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 13:29:41 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 8 Apr 2016 22:28:48 +0200 Message-Id: <1460147350-7601-29-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> References: <1460147350-7601-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH 28/50] explicitly include qom/cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP exec/cpu-all.h includes qom/cpu.h. Explicit inclusion will keep things working when cpu.h will not be included indirectly almost everywhere (either directly or through qemu-common.h). Signed-off-by: Paolo Bonzini --- hw/acpi/piix4.c | 1 + hw/arm/collie.c | 1 + hw/cpu/a9mpcore.c | 1 + hw/isa/lpc_ich9.c | 1 + include/hw/ppc/openpic.h | 1 + 5 files changed, 5 insertions(+) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 16abdf1..b3e3bb3 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -39,6 +39,7 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/xen/xen.h" +#include "qom/cpu.h" //#define DEBUG diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 8bb308a..2e69531 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -18,6 +18,7 @@ #include "hw/block/flash.h" #include "sysemu/block-backend.h" #include "exec/address-spaces.h" +#include "qom/cpu.h" static struct arm_boot_info collie_binfo = { .loader_start = SA_SDCS0, diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 5459ae8..f17f292 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/cpu/a9mpcore.h" +#include "qom/cpu.h" static void a9mp_priv_set_irq(void *opaque, int irq, int level) { diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 99cd3ba..4f8ca45 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -47,6 +47,7 @@ #include "hw/pci/pci_bus.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "qom/cpu.h" static int ich9_lpc_sci_irq(ICH9LPCState *lpc); diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h index ee67098..1cf188d 100644 --- a/include/hw/ppc/openpic.h +++ b/include/hw/ppc/openpic.h @@ -3,6 +3,7 @@ #include "qemu-common.h" #include "hw/qdev.h" +#include "qom/cpu.h" #define TYPE_OPENPIC "openpic"