From patchwork Fri Apr 15 14:23:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 8851551 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8B2839F1E6 for ; Fri, 15 Apr 2016 14:31:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC50F20373 for ; Fri, 15 Apr 2016 14:31:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF0D3202E9 for ; Fri, 15 Apr 2016 14:31:40 +0000 (UTC) Received: from localhost ([::1]:35235 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ar4ma-0007Iz-8u for patchwork-qemu-devel@patchwork.kernel.org; Fri, 15 Apr 2016 10:31:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ar4fF-0000hV-MO for qemu-devel@nongnu.org; Fri, 15 Apr 2016 10:24:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ar4fE-0007hI-5Y for qemu-devel@nongnu.org; Fri, 15 Apr 2016 10:24:05 -0400 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:37255) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ar4fD-0007gj-S1 for qemu-devel@nongnu.org; Fri, 15 Apr 2016 10:24:04 -0400 Received: by mail-wm0-x235.google.com with SMTP id n3so35023804wmn.0 for ; Fri, 15 Apr 2016 07:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EvcHf/r/mM+7zUeOwCDa/QR867CpCwQbykRyylRboCQ=; b=iYtBVDtFqAfyS8OMvLWy31GFpqS+9fvukkGuNR9hos78SZhqP9KA6OAfDwIlnSfs6i tUPvI7vcUBAk9AUI6HIc6GxePbcMYhbEeqNUSVCaA/k/Pdm1Ji4wiTwwprAa7OvZjGbW v1v0rERv7PICNEIWma4dfVXfqpBQd0Qk6uyAs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EvcHf/r/mM+7zUeOwCDa/QR867CpCwQbykRyylRboCQ=; b=R1HMrBxBPtmlmZa91xqfkVwax7ILQgNnqPWxOQpUCn9lNBzHCAAnHODjK7h5uF74DC qsFmirTOU/jGdhTiBTe/8g9laxTmTszcg67/Oay2taH+JxQxJOMAz/91QHrqIrFwCyQh fl53ZDzh2fUA/nFspehqJLYkDBr3U7QJKtCurvd++gpoMnUmA9YE5wMB8U/FPwDop78b jUcKnDSoj489vM1QK73Us3RObl/qBDH2kl8VZD+QoK+jk/YnoJGqxz7Yr7QDFDceQROh idQUDa9C/5DUHHY0mIZBwJMSj0z+qwgHcplYXY6znMQ+46yZbqf2vv/mPv7EKG/aSW3W qPxQ== X-Gm-Message-State: AOPr4FW6M5ZAl8n/Wy3P1j1HdasxcPrTCrkm0n2vXuF/GWGAqzPrElHuHltZfC7UmedPdgxk X-Received: by 10.28.131.195 with SMTP id f186mr4538810wmd.97.1460730242883; Fri, 15 Apr 2016 07:24:02 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id a16sm38854093wme.22.2016.04.15.07.23.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Apr 2016 07:23:54 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 037D93E0585; Fri, 15 Apr 2016 15:24:05 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, serge.fdrv@gmail.com, cota@braap.org Date: Fri, 15 Apr 2016 15:23:47 +0100 Message-Id: <1460730231-1184-10-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1460730231-1184-1-git-send-email-alex.bennee@linaro.org> References: <1460730231-1184-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RFC v1 08/12] cputlb: introduce tlb_flush_* async work. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, qemu-devel@nongnu.org, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: KONRAD Frederic Some architectures allow to flush the tlb of other VCPUs. This is not a problem when we have only one thread for all VCPUs but it definitely needs to be an asynchronous work when we are in true multithreaded work. This patch doesn't do anything to protect other cputlb function being called in MTTCG mode making cross vCPU changes. Signed-off-by: KONRAD Frederic [AJB: remove need for g_malloc on defer, make check fixes] Signed-off-by: Alex Bennée --- v1 - Remove tlb_flush_all just do the check in tlb_flush. - remove the need to g_malloc - tlb_flush calls direct if !cpu->created --- cputlb.c | 61 ++++++++++++++++++++++++++++++++++++++----------- include/exec/exec-all.h | 1 + 2 files changed, 49 insertions(+), 13 deletions(-) diff --git a/cputlb.c b/cputlb.c index 1412049..42a3b07 100644 --- a/cputlb.c +++ b/cputlb.c @@ -56,22 +56,14 @@ } \ } while (0) +/* We need a solution for stuffing 64 bit pointers in 32 bit ones if + * we care about this combination */ +QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(void *)); + /* statistics */ int tlb_flush_count; -/* NOTE: - * If flush_global is true (the usual case), flush all tlb entries. - * If flush_global is false, flush (at least) all tlb entries not - * marked global. - * - * Since QEMU doesn't currently implement a global/not-global flag - * for tlb entries, at the moment tlb_flush() will also flush all - * tlb entries in the flush_global == false case. This is OK because - * CPU architectures generally permit an implementation to drop - * entries from the TLB at any time, so flushing more entries than - * required is only an efficiency issue, not a correctness issue. - */ -void tlb_flush(CPUState *cpu, int flush_global) +static void tlb_flush_nocheck(CPUState *cpu, int flush_global) { CPUArchState *env = cpu->env_ptr; @@ -89,6 +81,34 @@ void tlb_flush(CPUState *cpu, int flush_global) env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; tlb_flush_count++; + /* atomic_mb_set(&cpu->pending_tlb_flush, 0); */ +} + +static void tlb_flush_global_async_work(CPUState *cpu, void *opaque) +{ + tlb_flush_nocheck(cpu, GPOINTER_TO_INT(opaque)); +} + +/* NOTE: + * If flush_global is true (the usual case), flush all tlb entries. + * If flush_global is false, flush (at least) all tlb entries not + * marked global. + * + * Since QEMU doesn't currently implement a global/not-global flag + * for tlb entries, at the moment tlb_flush() will also flush all + * tlb entries in the flush_global == false case. This is OK because + * CPU architectures generally permit an implementation to drop + * entries from the TLB at any time, so flushing more entries than + * required is only an efficiency issue, not a correctness issue. + */ +void tlb_flush(CPUState *cpu, int flush_global) +{ + if (cpu->created) { + async_run_on_cpu(cpu, tlb_flush_global_async_work, + GINT_TO_POINTER(flush_global)); + } else { + tlb_flush_nocheck(cpu, flush_global); + } } static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) @@ -222,6 +242,21 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) tb_flush_jmp_cache(cpu, addr); } +static void tlb_flush_page_async_work(CPUState *cpu, void *opaque) +{ + tlb_flush_page(cpu, GPOINTER_TO_UINT(opaque)); +} + +void tlb_flush_page_all(target_ulong addr) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + async_run_on_cpu(cpu, tlb_flush_page_async_work, + GUINT_TO_POINTER(addr)); + } +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9144ee0..f695577 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -190,6 +190,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr); +void tlb_flush_page_all(target_ulong addr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) {