From patchwork Mon May 2 12:33:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 8992131 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CD224BF29F for ; Mon, 2 May 2016 12:48:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1FDAF201FE for ; Mon, 2 May 2016 12:48:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E1E3201FA for ; Mon, 2 May 2016 12:48:04 +0000 (UTC) Received: from localhost ([::1]:36460 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axDGa-0002lp-GH for patchwork-qemu-devel@patchwork.kernel.org; Mon, 02 May 2016 08:48:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axD4G-0007NI-Ix for qemu-devel@nongnu.org; Mon, 02 May 2016 08:35:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1axD44-0000Bc-OD for qemu-devel@nongnu.org; Mon, 02 May 2016 08:35:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37955) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1axD44-00007T-G6 for qemu-devel@nongnu.org; Mon, 02 May 2016 08:35:04 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 65280C00B8E4 for ; Mon, 2 May 2016 12:34:53 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u42CXqcL000450; Mon, 2 May 2016 08:34:51 -0400 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Mon, 2 May 2016 14:33:43 +0200 Message-Id: <1462192431-146342-35-git-send-email-imammedo@redhat.com> In-Reply-To: <1462192431-146342-1-git-send-email-imammedo@redhat.com> References: <1462192431-146342-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC 34/42] acpi: cpuhp: add command and data registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, ehabkost@redhat.com, mst@redhat.com, armbru@redhat.com, marcel@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CPU device has a lot of optional methods that might be needed to be added in future in QEMU, so instead of reserving/consuming IO/MMIO register for each of it introduce a generic DATA read-write register which is multiplexed by additional COMMAND write-only register. currently that registers will be used for getting CPU's _PXM value and setting _OST.event/_OST.status values that OSPM reports to QEMU. Signed-off-by: Igor Mammedov --- hw/acpi/cpu.c | 26 ++++++++++++++++++++++++++ include/hw/acpi/cpu.h | 1 + trace-events | 1 + 3 files changed, 28 insertions(+) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index f61d5a8..a238ced 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -7,6 +7,12 @@ #define ACPI_CPU_HOTPLUG_REG_LEN 12 #define ACPI_CPU_SELECTOR_OFFSET_WR 0 #define ACPI_CPU_FLAGS_OFFSET_RW 4 +#define ACPI_CPU_CMD_OFFSET_WR 5 +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8 + +enum { + CPHP_CMD_MAX +}; static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr, unsigned size) { @@ -27,6 +33,12 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr, unsigned size) val |= cdev->is_removing ? 4 : 0; trace_cpuhp_acpi_read_flags(cpu_st->selector, val); break; + case ACPI_CPU_CMD_DATA_OFFSET_RW: + switch (cpu_st->command) { + default: + break; + } + break; default: break; } @@ -80,6 +92,12 @@ static void cpu_hotplug_wr(void *opaque, hwaddr addr, uint64_t data, } } break; + case ACPI_CPU_CMD_OFFSET_WR: + trace_cpuhp_acpi_write_cmd(cpu_st->selector, data); + if (data < CPHP_CMD_MAX) { + cpu_st->command = data; + } + break; default: break; } @@ -211,6 +229,7 @@ const VMStateDescription vmstate_cpu_hotplug = { .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(selector, CPUHotplugState), + VMSTATE_UINT32(command, CPUHotplugState), VMSTATE_STRUCT_VARRAY_POINTER_UINT32(devs, CPUHotplugState, dev_count, vmstate_cpuhp_sts, AcpiCpuStatus), VMSTATE_END_OF_LIST() @@ -230,6 +249,8 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_EJECT_EVENT "CEJ0" #define CPU_INSERT_EVENT "CINS" #define CPU_REMOVE_EVENT "CRMV" +#define CPU_COMMAND "CCMD" +#define CPU_DATA "CDAT" void build_cpus_aml(Aml *table, MachineState *machine, bool acpi1_compat, const char *res_root, const char *event_handler_method, @@ -281,11 +302,16 @@ void build_cpus_aml(Aml *table, MachineState *machine, bool acpi1_compat, aml_append(field, aml_named_field(CPU_REMOVE_EVENT, 1)); /* initiates device eject, write only */ aml_append(field, aml_named_field(CPU_EJECT_EVENT, 1)); + aml_append(field, aml_reserved_field(4)); + aml_append(field, aml_named_field(CPU_COMMAND, 8)); aml_append(cpu_ctrl_dev, field); field = aml_field("PRST", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); /* CPU selector, write only */ aml_append(field, aml_named_field(CPU_SELECTOR, 32)); + /* flags + cmd + 2byte align */ + aml_append(field, aml_reserved_field(4 * 8)); + aml_append(field, aml_named_field(CPU_DATA, 32)); aml_append(cpu_ctrl_dev, field); } diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 829114f..6de9476 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -29,6 +29,7 @@ typedef struct CPUHotplugState { MemoryRegion ctrl_reg; bool is_enabled; uint32_t selector; + uint32_t command; uint32_t dev_count; AcpiCpuStatus *devs; } CPUHotplugState; diff --git a/trace-events b/trace-events index 9df9531..108ae07 100644 --- a/trace-events +++ b/trace-events @@ -1916,5 +1916,6 @@ cpuhp_acpi_read_flags(uint32_t idx, uint8_t flags) "idx[0x%"PRIx32"] flags: 0x%" cpuhp_acpi_clear_inserting_evt(uint32_t idx) "idx[0x%"PRIx32"]" cpuhp_acpi_clear_remove_evt(uint32_t idx) "idx[0x%"PRIx32"]" cpuhp_acpi_write_idx(uint32_t idx) "set active cpu idx: 0x%"PRIx32 +cpuhp_acpi_write_cmd(uint32_t idx, uint8_t cmd) "idx[0x%"PRIx32"] cmd: 0x%"PRIx8 cpuhp_acpi_ejecting_invalid_cpu(uint32_t idx) "0x%"PRIx32 cpuhp_acpi_ejecting_cpu(uint32_t idx) "0x%"PRIx32