From patchwork Mon May 9 17:29:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9048421 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D9AAE9F1D3 for ; Mon, 9 May 2016 17:30:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 482D220114 for ; Mon, 9 May 2016 17:30:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9724F20103 for ; Mon, 9 May 2016 17:30:42 +0000 (UTC) Received: from localhost ([::1]:42473 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azp0y-0004BL-OJ for patchwork-qemu-devel@patchwork.kernel.org; Mon, 09 May 2016 13:30:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azp0g-00040k-Ni for qemu-devel@nongnu.org; Mon, 09 May 2016 13:30:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1azp0e-0000Hw-P7 for qemu-devel@nongnu.org; Mon, 09 May 2016 13:30:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:56751) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azp0c-00005k-Hd; Mon, 09 May 2016 13:30:18 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1azp0O-0001W1-0X; Mon, 09 May 2016 18:30:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 9 May 2016 18:29:47 +0100 Message-Id: <1462814989-24360-22-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462814989-24360-1-git-send-email-peter.maydell@linaro.org> References: <1462814989-24360-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org, Shlomo Pongratz , Shlomo Pongratz , Pavel Fedin , Shannon Zhao , Christoffer Dall Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Linux kernel's GICv3 driver assumes that all interrupts are in group 1. This is correct if the system supports the Security extensions, because in that case the kernel cannot configure the interrupts and it must have been done already by firmware. However if the system does not support the Security extensions then the kernel is perfectly capable of configuring them into group 1 itself if it wants them there; it just doesn't. Work around this by having the GICv3 emulation put all the interrupts into group 1 if we're directly booting a Linux kernel, whether the Security extensions are supported or not. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 901ec60..73d3c6d 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -288,6 +288,13 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, * equivalent). */ s->irq_reset_nonsecure = true; + } else { + /* This is purely a workaround for broken Linux kernel behaviour + * on non-TrustZone systems. It assumes that interrupts have been + * set to group 1 even though it could do that itself for a non-secure + * GIC. + */ + s->irq_reset_nonsecure = true; } }